NVMCON1
1
.1
’ by the user in order to implement test sequences.Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NVMREGS | LWLO | FREE | WRERR | WREN | WR | RD | |
Access | R/W | R/W | R/S/HC | R/W/HS | R/W | R/S/HC | R/S/HC |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
NVM Region Selection bit
Value | Description |
---|---|
1 | Access DIA, DCI, Configuration, User ID, Revision ID, and Device ID Registers |
0 | Access Program Flash Memory |
Load Write Latches Only bit
Value | Name | Description |
---|---|---|
1 | When FREE = 0 |
The next WR command updates the write latch for this word within the row; no memory operation is initiated. |
0 | When FREE = 0 |
The next WR command writes data or erases |
- | Otherwise: | This bit is ignored. |
Program Flash Memory Erase Enable bit
Value | Description |
---|---|
1 | Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated address is erased (to all 1s) to prepare for writing. |
0 | The next WR command writes without erasing. |
Value | Description |
---|---|
1 | A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one while NVMADR points to a write-protected address. |
0 | All write operations have completed normally. |
Program/Erase Enable bit
Value | Description |
---|---|
1 | Allows program/erase cycles |
0 | Inhibits programming/erasing of program Flash |
Value | Description |
---|---|
1 | Initiates the operation indicated by table in “WRERR Bit” section. |
0 | NVM program/erase operation is complete and inactive. |
Read Control bit
Value | Description |
---|---|
1 | Initiates a read at address = NVMADR, and loads data to NVMDAT Read takes one instruction cycle and the bit is cleared when the operation is complete. The bit can only be set (not cleared) in software. |
0 | NVM read operation is complete and inactive |