NVMCON1

Nonvolatile Memory Control 1 Register
Notes:
  1. 1.Bit is undefined while WR = 1.
  2. 2.Bit must be cleared by software; hardware will not clear this bit.
  3. 3.Bit may be written to ‘1’ by the user in order to implement test sequences.
  4. 4.This bit can only be set by following the sequence described in the “NVM Unlock Sequence” section.
  5. 5.Operations are self-timed and the WR bit is cleared by hardware when complete.
  6. 6.Once a write operation is initiated, setting this bit to zero will have no effect.
Name:
NVMCON1
Address:
0x81E
Reset:
Access:
Bit76543210
NVMREGSLWLOFREEWRERRWRENWRRD
AccessR/WR/WR/S/HCR/W/HSR/WR/S/HCR/S/HC
Reset0000000

Bit 6 – NVMREGS: NVM Region Selection bit

NVM Region Selection bit

ValueDescription
1 Access DIA, DCI, Configuration, User ID, Revision ID, and Device ID Registers
0 Access Program Flash Memory

Bit 5 – LWLO: Load Write Latches Only bit

Load Write Latches Only bit

ValueNameDescription
1 When FREE = 0 The next WR command updates the write latch for this word within the row; no memory operation is initiated.
0 When FREE = 0 The next WR command writes data or erases
- Otherwise: This bit is ignored.

Bit 4 – FREE: Program Flash Memory Erase Enable bit

Program Flash Memory Erase Enable bit

ValueDescription
1 Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated address is erased (to all 1s) to prepare for writing.
0 The next WR command writes without erasing.

Bit 3 – WRERR

Write-Reset Error Flag bit(1,2,3)
ValueDescription
1 A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one while NVMADR points to a write-protected address.
0 All write operations have completed normally.

Bit 2 – WREN: Program/Erase Enable bit

Program/Erase Enable bit

ValueDescription
1 Allows program/erase cycles
0 Inhibits programming/erasing of program Flash

Bit 1 – WR: Write Control bit(4,5,6)

Write Control bit(4,5,6)

ValueDescription
1 Initiates the operation indicated by table in “WRERR Bit” section.
0 NVM program/erase operation is complete and inactive.

Bit 0 – RD: Read Control bit

Read Control bit

ValueDescription
1 Initiates a read at address = NVMADR, and loads data to NVMDAT Read takes one instruction cycle and the bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.
0 NVM read operation is complete and inactive