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# 2.60 L2 Cache Controller (L2CC)

The L2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM multiway cache macrocell, version r3p2. The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a method of improving the system performance when significant memory traffic is generated by the processor.

## Using The Library

The interface to L2 Cache operations is defined in the plib_l2cc.h header file. By definition a secondary cache assumes the presence of a Level 1 or primary cache, closely coupled or internal to the processor. Memory access is fastest to L1 cache, followed closely by L2 cache.

Cache Coherency

Cache coherency is the discipline of ensuring that the data stored in main memory matches the corresponding data in the cache. The majority of the cache-related APIs deal with cache coherency. These functions allow the user to flush, clean and invalidate entire cache(s), or just a range of addresses within the cache.

Caches most often lose coherency when a bus master other than the CPU modifies memory. This happens frequently with DMA. Two examples are provided in the following section.

Example 1

Imagine a situation where you would like to transfer data from a source buffer to a destination buffer using DMA. You would write data to the source buffer, start the DMA transfer, and then expect that the same data now appears in the destination buffer. With the cache in write-back mode, this will not be the case. When transferring data out of memory using DMA, it is possible that the desired data is held in the cache, but has never been written back to main memory. Therefore, in this case, you write data to the source buffer and it gets stored in cache. When the DMA transfer executes, it will pull the data from the source buffer out of RAM and then transfer it to the destination buffer in RAM. The problem is that the fresh data was stored in the cache but never written back to RAM, so what has happened is that stale data was copied over rather than the intended data. What is needed is a way to force the cache to write its data back to main memory before the DMA transfer. This is known as a write-back operation and would be performed with the use of the function: DCACHE_CLEAN_BY_ADDR(addr,sz). This cleans L1 and L2 caches by invoking dcache_CleanByAddr(addr,sz) and PLIB_L2CC_CleanCacheByAddr(addr,sz) functions.

Example 2

The second situation involves writing data into memory using DMA. Imagine that the cache is holding a chunk of data known as destination_buffer. You then execute a DMA transfer to copy some new data from a source buffer into destination_buffer. The issue here is that main memory now contains the correct data, but the cache holds a copy of stale data for destination_buffer. The CPU cannot see this problem and it will keep pulling the data out of the cache, not even realizing that it’s stale. What is needed is a way to tell the cache to pull the fresh data out of main memory, to replace the stale data that the cache contains. This is known as an invalidate operation. It is performed with the use of the function: DCACHE_INVALIDATE_BY_ADDR(addr,sz). This invalidates L1 and L2 caches by invoking PLIB_L2CC_InvalidateCacheByAddr(addr,sz) and dcache_InvalidateByAddr(addr,sz) functions.

The example application, cache_maintenance, in the Cache PLIB Examples demonstrates this situation and shows how to resolve the issue.

## Library Interface

L2 Cache Controller peripheral library provides the following interfaces:

Functions

Name | Description
--- | ---
PLIB_L2CC_Initialize | Initialize the L2 cache controller
PLIB_L2CC_CleanCache | Cleans (flushes) the L2 cache
PLIB_L2CC_InvalidateCache | Invalidates L2 cache entries
PLIB_L2CC_CleanInvalidateCache | Cleans and Invalidates L2 cache entries
PLIB_L2CC_InvalidateCacheByAddr | Invalidates L2 cache entries
PLIB_L2CC_CleanCacheByAddr | Flushes L2 cache entries
PLIB_L2CC_CleanInvalidateCacheByAddr | Cleans and Invalidates L2 cache entries

Note: Not all APIs maybe implemented. See the specific device family section for available APIs.