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# 3.45.24 Extensible DMA Controller (XDMAC)

The DMA Controller (XDMAC) can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. The XDMAC has several DMA channels and each channel is fully programmable and provides both peripheral, or memory-to-memory transfers.

## Using The Library

The XDMA controller requires a source address, destination address and transfer count to initiate the transfer. It transfers data on each DMA trigger and decrements the transfer count. The DMA generates completion interrupt to notify the CPU at the end of the DMA transfer.

The user can use either the callback mechanism or the polling mechanism to determine DMA completion.

- With polling, the application will need to continuously poll to check if the DMA has completed the transfer.

- With callback, the registered callback function will be called when the transfer is completed. This means the application do not have to poll continuously.

Callback method

This following example demonstrates a DMA transfer with callback.

    #define USART1_TRANSMIT_ADDRESS     (&USART1_REGS->US_THR)

    uint8_t txBuffer[] = "Hello World!";

    void XDMAC_Callback(XDMAC_TRANSFER_EVENT status, uintptr_t context)
    {
          if(status == XDMAC_TRANSFER_COMPLETE)
          {
               // Transfer is completed.
          }
    }

     int main ( void )
    {
          SYS_Initialize ( NULL );

          XDMAC_ChannelCallbackRegister(XDMAC_CHANNEL_0, XDMAC_Callback, 0);

          XDMAC_ChannelTransfer(XDMAC_CHANNEL_0, txBuffer, (const void *)USART1_TRANSMIT_ADDRESS, sizeof(txBuffer));

    }

Polling method

The following example demonstrates a DMA transfer with polling.

    #define USART1_TRANSMIT_ADDRESS     (&USART1_REGS->US_THR)

    uint8_t txBuffer[] = "Hello World!";

    int main ( void )
    {
          SYS_Initialize ( NULL );

          XDMAC_ChannelTransfer(XDMAC_CHANNEL_0, txBuffer, (const void *)USART1_TRANSMIT_ADDRESS, sizeof(txBuffer));

          while(XDMAC_ChannelIsBusy(XDMAC_CHANNEL_0));
    }

## Library Interface

Extensible DMA Controller peripheral library provides the following interfaces:

Functions

Name | Description
--- | ---
XDMAC_Initialize | Initializes the XDMAC controller of the device
XDMAC_ChannelCallbackRegister | This function allows a XDMAC PLIB client to set an event handler
XDMAC_ChannelTransfer | Adds a data transfer to a XDMAC channel and enables the channel to start data transfer
XDMAC_ChannelLinkedListTransfer | Sets up a multi-block data transfer on a specified XDMAC channel using linked list feature
XDMAC_ChannelIsBusy | Returns the busy status of a specific XDMAC Channel
XDMAC_ChannelTransferStatusGet | Returns the XDMAC channel's transfer status
XDMAC_ChannelDisable | Disables the specified channel
XDMAC_ChannelSettingsGet | Returns the channel settings of a specific XDMAC Channel
XDMAC_ChannelSettingsSet | Sets the channel settings of a specific XDMAC Channel
XDMAC_ChannelBlockLengthSet | Sets the channel Block Length of a specific XDMAC Channel
XDMAC_ChannelSuspend | This function Suspends the DMA channel
XDMAC_ChannelResume | This function Resumes the DMA channel

Data types and constants

Name | Type | Description
--- | --- | ---
XDMAC_CHANNEL | Enum | Lists the set of channels available for data transfer using DMAC
XDMAC_TRANSFER_EVENT | Enum | Enumeration of possible DMAC transfer events
XDMAC_CHANNEL_CALLBACK | Typedef | Pointer to a DMAC Transfer Event handler function
XDMAC_CHANNEL_CONFIG | Typedef | DMAC Block Transfer Control configuration value
XDMAC_DESCRIPTOR_CONTROL | Union | Defines the descriptor control for linked list operation
XDMAC_DESCRIPTOR_VIEW_0 | Struct | Defines the descriptor view 0 available for master transfer
XDMAC_DESCRIPTOR_VIEW_1 | Struct | Defines the descriptor view 1 available for master transfer
XDMAC_DESCRIPTOR_VIEW_2 | Struct | Defines the descriptor view 2 available for master transfer
XDMAC_DESCRIPTOR_VIEW_3 | Struct | Defines the descriptor view 3 available for master transfer
XDMAC_MICRO_BLOCK_CONTROL | Struct | Defines the control parameters for linked list operation