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# 3.32.3 Clock Generator (CLOCK)

The Clock Generator user interface is embedded within the Power Management Controller. The Clock system generates and distributes the clock for the processor and peripherals.

Clock Generators:

The Clock Generator is made up of:

- Oscillators

  - A low-power 32.768 kHz oscillator supporting crystal and resonators (referred to as "32.768 kHz crystal oscillator" throughout the document)

  - An embedded always-on, slow RC oscillator generating a typical 32 kHz clock

  - A 12 to 50 MHz oscillator supporting crystals, resonators and Bypass mode (referred to as "main crystal oscillator" throughout the document)

  - A main RC oscillator generating a typical 12 MHz clock

- A set of 7 fractional-N PLLs with an input frequency range of 12 to 50 MHz and an internal frequency range of 600 to 1200 MHz, namely:

  - CPUPLL

  - SYSPLL

  - DDRPLL

  - IMGPLL

  - BAUDPLL

  - AUDIOPLL

  - ETHPLL

The Clock Generator provides the following clocks:

- MD_SLCK-Monitoring domain slow clock. This clock, sourced from the always-on slow RC oscillator only, is the only permanent clock of the system and feeds safety-critical functions of the device (WDT, RSTC, SCKC, frequency monitors and detectors, PMC startup time counters).

- TD_SLCK-Timing domain slow clock. This clock, sourced from the 32.768 kHz crystal oscillator or the always-on slow RC oscillator, is routed to the RTC and RTT peripherals.

- MAINCK-Output of the main clock oscillator selection. This clock is either the main crystal oscillator or the main RC oscillator.

- PLL Clocks-Outputs of embedded PLLs

The Power Management Controller provides the following clocks:

- Main System Bus Clocks (MCKx)-clock signals that are the root clock of a group of peripherals. They are programmable from a few hundred Hz to the maximum operating frequency of the peripheral group. MCK0 is the main system bus clock associated to all peripherals that are synchronous with the processor.

- Processor Clock (CPU_CLK)-can be tuned through a frequency scaler module and automatically switched off when entering the processor in Sleep mode.

- Free-running Processor Clock (FCLK)-the source clock of CPU_CLK. Is not affected when Sleep mode or the frequency scaler is activated.

- Peripheral Clocks with independent on/off control, provided to the peripherals. Each peripheral clock is inherited from one of the MCKx clocks.

- Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCKx pins.

- Generic Clock (GCLK) with controllable division and on/off control, independent of MCKx and CPU_CLK. Provided to selected peripherals. Refer to the table "Peripheral Identifiers" for more details on GCLK availability per peripheral.

## Using The Library

The Clock peripheral library initializes the clock system as configured by the user in the MCC Clock configurator. It can be accessed via the "Tools" drop down of the MPLAB Code Configurator menu bar.

## Library Interface

Clock Generator peripheral library provides the following interfaces:

Functions

Name | Description
--- | ---
CLK_Initialize | Initializes hardware of the System Clock and Peripheral Clock