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# 3.37.12 Power Manager (PM)

The Power Manager (PM) consists of three modules: the synchronous clock controller, the sleep controller, and the reset controller. These modules are responsible for distributing clocks, supervising low power modes, and administering the MCU's resets.

Sleep Controller

In active mode, all clock domains are active, allowing software execution and peripheral operation. The Sleep Mode Controller allows the user to choose between different sleep modes depending on application requirements, to save power.

There are two main types of sleep modes available::

- Idle sleep mode: The CPU stops executing code, no peripheral are disabled. All interrupt sources can wake up the device

- Standby sleep mode: The user can configure peripherals to be enabled or not using the respective RUNSTDBY bit. This means that power consumption is highly dependent on what functionality is enabled.

Three are three levels of idle mode:

- Idle 0: The CPU clock domain is stopped

- Idle 1: The CPU and AHB clock domains are stopped

- Idle 2: The CPU, AHB and APB clock domains are stopped

Reset Controller

The Reset Controller collects the various reset sources and generates reset for the device and allows the reset source to be identified by the software.

- Power On Reset: The device contains a power-on-reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device.

- VDDCORE Brown Out Reset: BOD12 will reset the device if a voltage of 1.2 V or below is observed on the I/O pin supplying power to the MCU core (VDDCORE).

- VDDANA Brown Out Reset: BOD33 resets the device if the voltage on the VDDANA pin falls below a value configured by the SYSCTRL

- Watchdog Reset: The watchdog reset occurs when it times out

- System Reset: The System Reset Request is a software reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU

- External Reset: A external reset is generated when a low level is detected on the RESET pin

Resets are divided into two modes based upon the source of the reset.

- Power Resets include resets generated by POR, BOD12, and BOD33.

- User Resets consist of the external reset, WDT, and the software reset instruction

Both power and user reset causes the device to restart and set most registers of the MCU to a preset state. The difference between the two modes is how they affect the Real Time Clock, the 32 K oscillator, and the WDT. The underlying reasoning for having two reset modes is to protect the operation of the WDT and the RTC from non-power related anomalies.

Synchronous Clock Controller

The main clock is s the common root for the synchronous clocks. This is fed into the common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx modules.

## Using The Library

The power manager peripheral library provides API to enter Idle Sleep mode and Standby Sleep mode. It also provides API to find the cause of last device reset

## Library Interface

Power Manager peripheral library provides the following interfaces:

Functions

Name | Description
--- | ---
PM_ResetCauseGet | Reports the cause of the last reset
PM_StandbyModeEnter | Puts the device in standby mode
PM_IdleModeEnter | Puts the device in Idle mode

Data types and constants

Name | Type | Description
--- | --- | ---
PM_RESET_CAUSE | Enum | Identifies the type of reset