oxy_webhelp_navlinks = {"GUID-F8796A23-EC6C-4485-A46D-BD85FDFEA48C-d1890e27":{"topics":[{"title":"<ph>1.1.1.1<\/ph>\nBasic Memory Layout for Cortex-M Based MCUs","href":"GUID-222D822A-B2E5-41CF-8023-83880E0B29FE.html","attributes":{"data-id":"GUID-222D822A-B2E5-41CF-8023-83880E0B29FE"},"menu":{"hasChildren":false},"tocID":"GUID-222D822A-B2E5-41CF-8023-83880E0B29FE-d1890e35","topics":[]},{"title":"<ph>1.1.1.2<\/ph>\nBasic Memory Layout for MIPS Based MCUs","href":"GUID-F59CD389-FA8E-4FBC-B8E7-F88E3D2FE22A.html","attributes":{"data-id":"GUID-F59CD389-FA8E-4FBC-B8E7-F88E3D2FE22A"},"menu":{"hasChildren":false},"tocID":"GUID-F59CD389-FA8E-4FBC-B8E7-F88E3D2FE22A-d1890e43","topics":[]},{"title":"<ph>1.1.1.3<\/ph>\nFail Safe Update Memory Layout for Cortex-M Based MCUs","href":"GUID-0356B3ED-662E-4B3F-986B-B69F09ABA66A.html","attributes":{"data-id":"GUID-0356B3ED-662E-4B3F-986B-B69F09ABA66A"},"menu":{"hasChildren":false},"tocID":"GUID-0356B3ED-662E-4B3F-986B-B69F09ABA66A-d1890e51","topics":[]},{"title":"<ph>1.1.1.4<\/ph>\nFail Safe Update Memory Layout for MIPS Based MCUs","href":"GUID-ED3329AE-AA04-4537-B8D5-422A4114845D.html","attributes":{"data-id":"GUID-ED3329AE-AA04-4537-B8D5-422A4114845D"},"menu":{"hasChildren":false},"tocID":"GUID-ED3329AE-AA04-4537-B8D5-422A4114845D-d1890e59","topics":[]},{"title":"<ph>1.1.1.5<\/ph>\nMPU Bootloader Memory Layout","href":"GUID-F84CD2CC-E751-475A-89F0-AF8FE4C58714.html","attributes":{"data-id":"GUID-F84CD2CC-E751-475A-89F0-AF8FE4C58714"},"menu":{"hasChildren":false},"tocID":"GUID-F84CD2CC-E751-475A-89F0-AF8FE4C58714-d1890e67","topics":[]},{"title":"<ph>1.1.1.6<\/ph>\nUART Bootloader Protocol","href":"GUID-70530E39-2BD7-49C8-96C4-E41A9CCA9A74.html","attributes":{"data-id":"GUID-70530E39-2BD7-49C8-96C4-E41A9CCA9A74"},"menu":{"hasChildren":false},"tocID":"GUID-70530E39-2BD7-49C8-96C4-E41A9CCA9A74-d1890e75","next":"GUID-70530E39-2BD7-49C8-96C4-E41A9CCA9A74-d1890e75"}]}};