oxy_webhelp_navlinks = {"how-the-uart-bootloader-library-works-d1857e27":{"topics":[{"title":"<ph>1.1.1.1<\/ph>\nBasic Memory layout for CORTEX-M based MCUs","href":"GUID-8DC24BD7-3112-401A-A207-3A1FC3A416AB.html","attributes":{"data-id":"basic-memory-layout-for-cortex-m-based-mcus"},"menu":{"hasChildren":false},"tocID":"basic-memory-layout-for-cortex-m-based-mcus-d1857e35","topics":[]},{"title":"<ph>1.1.1.2<\/ph>\nBasic Memory layout for MIPS based MCUs","href":"GUID-C2AA810E-4247-4971-99CA-8F3D78A9DD2F.html","attributes":{"data-id":"basic-memory-layout-for-mips-based-mcus"},"menu":{"hasChildren":false},"tocID":"basic-memory-layout-for-mips-based-mcus-d1857e43","topics":[]},{"title":"<ph>1.1.1.3<\/ph>\nFail Safe Update Memory layout for CORTEX-M based MCUs","href":"GUID-A6CA4BD5-4F43-4E12-8624-3AA1328B3DFE.html","attributes":{"data-id":"fail-safe-update-memory-layout-for-cortex-m-based-mcus"},"menu":{"hasChildren":false},"tocID":"fail-safe-update-memory-layout-for-cortex-m-based-mcus-d1857e51","topics":[]},{"title":"<ph>1.1.1.4<\/ph>\nFail Safe Update Memory layout for MIPS based MCUs","href":"GUID-CFBAB2D2-47E5-4A1D-AD31-BBCA6C7FC3A9.html","attributes":{"data-id":"fail-safe-update-memory-layout-for-mips-based-mcus"},"menu":{"hasChildren":false},"tocID":"fail-safe-update-memory-layout-for-mips-based-mcus-d1857e59","topics":[]},{"title":"<ph>1.1.1.5<\/ph>\nMPU Bootloader memory layout","href":"GUID-3FF9147C-59F3-4949-BFF1-3A00E90B972B.html","attributes":{"data-id":"mpu-bootloader-memory-layout"},"menu":{"hasChildren":false},"tocID":"mpu-bootloader-memory-layout-d1857e67","topics":[]},{"title":"<ph>1.1.1.6<\/ph>\nUART Bootloader Protocol","href":"GUID-8828D474-F227-4FE0-88EE-135AA591750F.html","attributes":{"data-id":"uart-bootloader-protocol"},"menu":{"hasChildren":false},"tocID":"uart-bootloader-protocol-d1857e75","next":"uart-bootloader-protocol-d1857e75"}]}};