Jump to main content

##

# 4 Initializing MSS DDR4

(Ask a Question)

Automatic initialization of the DDR4 memory (for hardened MSS DDR controller only) involves the following steps:
Training logic performs HS_IO_CLK-to-SYS_CLK training. Training logic performs CMD/ADDR to REF_CLK training. DDR controller waits for the PHY to be ready. At this point, it is assumed that the PHY outputs stable clocks. Controller asserts RESET_N, and CKE is held LOW. Controller deasserts RESET_N after 200 μs, and it then deasserts CKE after an additional 600 μs. Controller waits for tXPR. Controller writes to Register Command Words (RCW) and Buffer Control Words (BCW) if RDIMM/LRDIMM is used. MRS command is sent to the following mode registers (in order): MR3, MR6, MR5, MR4, MR2, MR1, and MR0. Controller waits for 128 clock cycles (geardown mode). Controller waits for an additional 512 clock cycles. During this wait time, the ZQCL (long) command is sent to each rank independently to calibrate the Internal Resistance Termination (RTT) and Output Driver Impedance (RON) values. Training logic performs CMD/ADDR to REF_CLK training. Training logic performs write leveling. Training logic performs Read Gate (Read DQS gate) training. Training logic aligns Read Data (DQ) bits. Training logic aligns Read Data Strobe (DQS) to DQ. Write calibration is performed. Sanity check is performed. Normal operation begins. |