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# 3.5 Read DQDQS Training Fail

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This section describes the probable reasons for the read DQDQS training failure and the checks required to ensure that the training passes.

## 3.5.1 Read DQDQS Training Fail—Check 1

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Possible Reason
  Signal integrity issues on DQ or DQS lines. When check 1 of the Read DQDQS training fails, a dialog box appears as shown in the following figure.
  Figure 3-14.Read DQDQS Training

Workaround
  Configure any one of the following parameters to a different value using the MSS Configurator when check 1 of the Read DQDQS training fails:
  - Decrease the FPGA DQDQS start training window offset
  - FPGA DQ ODT
  - FPGA Vref Data
  - Memory Pull-Down Drive Strength

  The following figure shows the configuration of DQ ODT, DQDQS start training window offset, or Vref data in the DDR Controller tab.

  Figure 3-15.Configuring DQ ODT, DQDQS Start Training Window Offset, or Vref Data—DDR Controller Tab

  The following figure shows the configuration of pull-down drive strength in the DDR Memory Initialization tab.

  Figure 3-16.Configuring Pull-Down Drive Strength—DDR Memory Initialization Tab

## 3.5.2 Read DQDQS Training Fail—Check 2

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Possible Reason
  Signal integrity issues on DQ or wrong start training window offset. When check 2 of the Read DQDQS training fails, a dialog box appears as shown in the following figure.
  Figure 3-17.Read DQDQS Training

Workaround
  Configure any one of the following parameters to a different value using the MSS Configurator when check 2 of the Read DQDQS training fails:
  - FPGA DQ ODT
  - FPGA Vref Data
  - Memory Pull-Down Drive Strength
  The following figure shows the configuration of DQ ODT or Vref data in the DDR Controller tab.
  Figure 3-18.Configuring DQ ODT or Vref Data—DDR Controller Tab
  The following figure shows the configuration of pull-down drive strength in the DDR Memory Initialization tab.
  Figure 3-19.Configuring Pull-Down Drive Strength—DDR Memory Initialization Tab

## 3.5.3 Read DQDQS Training Fail—Check 3

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Possible Reason
  Signal integrity issues on DQ or wrong start training window offset. When check 3 of the Read DQDQS training fails, a dialog box appears as shown in the following figure.
  Figure 3-20.Read DQDQS Training

Workaround
  Increase the FPGA DQDQS start training window offset value when check 3 of the Read DQDQS training fails, see the following figures.
  Figure 3-21.Configuring DQDQS Start Training Window Offset—DDR Controller Tab