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# 2 Initializing MSS LPDDR4

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Automatic initialization of the LPDDR4 memory (for hardened MSS DDR controller only) involves the following steps:
Training logic performs HS_IO_CLK-to-SYS_CLK training. DDR controller waits for the PHY to be ready. At this point, it is assumed that the PHY outputs stable clocks and signal levels. Controller asserts RESET_N, and CKE is held LOW. Controller deasserts RESET_N after 200 μs, and then deasserts CKE after an additional 2 ms. Controller waits for tXPR. MRS command is sent to the following mode registers (in order): MR13, MR1, MR2, MR3, MR4, MR11, MR16, MR17, MR22, and MR13. Controller waits for 512 clock cycles. During this wait time, the ZQCL (long) command is sent to each rank independently to calibrate the internal resistance termination (RTT) and output driver impedance (RON) values. Training logic performs CMD/ADDR to REF_CLK training. Training logic performs write leveling. Training logic performs Read Gate (Read DQS gate) training. Training logic aligns read data (DQ) bits. Training logic aligns read data strobe (DQS) to DQ. Write calibration is performed. Sanity check is performed. Normal operation begins. |