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# 1.1.2.3 Configuring the Library

## G3 MAC RT Driver Specific User Configurations

G3 MAC RT Driver library is configured through MCC. Below is a brief description and some figures of the MCC configuration window for G3 MAC RT driver.

The following figures show configuration for PL460 and PL360.
Figure 1-23.PL460 Configuration Options
Figure 1-24.PL360 Configuration Options

- PLC Driver Mode:
  - Specifies the PLC device physically connected (PL360 or PL460)
  - The pins in use will vary depending on the device selected
- RTOS Settings:
  - Stack Size (in bytes):
    - Specifies the number of bytes to be allocated on the stack for the driver task
  - Task Priority:
    - Specifies priority for the driver task thread. The value can vary based on RTOS used.
- PLIB Used:
  - Indicates the SPI peripheral instance used by the G3 MAC RT driver
  - The name of the peripheral will vary from device to device
- SPI NPCS Used:
  - SPI chip select line to be used by the G3 MAC RT driver
  - It is only visible if the connected peripheral supports multiple chip select lines
- External Interrupt Pin:
  - GPIO pin to be used as external interrupt interface (active low)
  - This pin automatically indicates that the firmware running in the PLC device has one or more pending events to be consulted
  - This pin must be configured as GPIO input in Pin Settings configuration. Set Pull Down and Low Level Interrupt configuration:
    Figure 1-25.PLC PIO Interrupt Settings
- Reset Pin:
  - GPIO pin to be used as reset (active low)
  - This pin resets the core and the peripherals of the PLC device
  - This pin must be configured as GPIO output in Pin Settings configuration
- LDO Enable Control:
  - Enables the LDO Enable pin control. LDO Enable signal of PLC transceiver can be controlled from driver.
  - LDO Enable Pin:
    - GPIO pin to be used as LDO enable (active high)
    - This pin provides power to the core voltage regulator embedded in the PLC device
    - This pin must be configured as GPIO output in Pin Settings configuration
    Note: This pin is disabled by default. Latest revisions of PL460-EK connect LDO Enable to 3V3 to fix a permanent high level, which is the recommended configuration.
- TX Enable Pin:
  - GPIO pin to allow PLC transmissions (active high)
  - This pin must be configured as GPIO output in Pin Settings configuration
  - It is only visible if PLC Driver mode is configured as PL460
- Sleep Mode:
  - Enables the Sleep mode. In Sleep mode, the core and peripherals of the PLC device are reset, reducing power consumption.
  - Standby Pin:
    - GPIO pin to be used as Sleep mode enable (active high)
    - This pin must be configured as GPIO output in Pin Settings configuration
    - It is only visible if Sleep mode is enabled
    Note: This pin is disabled by default. Latest revisions of PL460-EK connect STBY to GND to fix a permanent low level, which is the recommended configuration.
- Thermal Monitor:
  - Enables Thermal Monitor. It allows to check the Thermal Monitor pin of PL460 and not allow transmissions if Thermal Warning is indicated.
  - It is only visible if PLC Driver mode is configured as PL460.
  - Thermal Monitor Pin:
    - GPIO pin to check the status of the Thermal monitor
    - This pin must be configured as GPIO input in Pin Settings configuration. Set Pull Up configuration
    - It is only visible if Thermal Monitor is enabled
- PLC Coupling Settings:
  - PLC Driver mode must have been selected before obtaining a valid PLC coupling settings
  - Used to establish the hardware configuration associated to the PLC frequency bands to use
  - The options of this configuration will vary from the selected PLC Driver mode
  - PL460:
    - Main Branch:
      Figure 1-26.PL460: Hardware Blocks in a Single Band
      - The Main Transmission Branch uses the embedded class-D PLC line driver to optimize performance in terms of efficiency and EMC compliance, while reducing BOM cost and PCB complexity
      - This is the default branch for single-band applications either in CENELEC-A, CENELEC-B or FCC bands
      - With FCC High Attenuation Branch, the PL460 is capable of automatically managing two external filters in the filtering stage, each filter associated to an ASOx line
    - Auxiliary Branch:
      Figure 1-27.PL460: Hardware Blocks in Multiband
      - The Auxiliary Transmission Branch can provide an additional output bit-stream, if required
      - The Auxiliary Transmission path cannot use the embedded PLC driver in the PL460 and requires an external circuit for signal amplification, in addition to the standard filtering and coupling stages
      - CENELEC-A or CENELEC-B bands are available with the Auxiliary Transmission Branch
  - PL360:
    - Single Branch:
      Figure 1-28.PL360: Hardware Blocks in a Single Branch With External Coupling
      - This is the default branch for single-band applications either in CENELEC-A (PLCOUP007) or CENELEC-B (PLCOUP014)
    - Double Branch:
      Figure 1-29.PL360: Hardware Blocks in Double Branch With External Coupling
      - This coupling configuration is used for FCC (PLCOUP006) or Multiband FCC & CENELEC-A (PLCOUP011)
    - Internal Driver:
      Figure 1-30.PL360: Hardware Blocks in a Single Band With Internal Coupling
      - In case of using a coupling with internal driver, only one branch is allowed and all the four EMIT pins must be connected to the same point and transmission control is indicated by TXRX0
      - This branch can be used for CENELEC-B (PLCOUP012)
  - CENELEC-A, CENELEC-B and FCC bands are available in G3-PLC:
    Figure 1-31.G3-PLC Frequency Table
  - PLC Coupling and Band Settings:
    - It selects the PLC Coupling variant used and consequently the G3-PLC PHY band or bands
    - The available options will vary depending on the PLC Driver mode selected
    - PL460:
      - CEN-A (CENELEC-A only; main branch)
      - CEN-B (CENELEC-B only; main branch)
      - FCC default (FCC only; main branch)
      - FCC high attenuation (FCC only; main branch)
      - Multiband FCC default & CEN-A (FCC + CENELEC-A; main branch + auxiliary branch)
      - Multiband FCC default & CEN-A (CENELEC-A only; auxiliary branch)
      - Multiband FCC default & CEN-B (FCC + CENELEC-B; main branch + auxiliary branch)
      - Multiband FCC default & CEN-B (CENELEC-B only; auxiliary branch)
      - Multiband FCC high attenuation & CEN-A (FCC + CENELEC-A; main branch + auxiliary branch)
      - Multiband FCC high attenuation & CEN-A (CENELEC-A only; auxiliary branch)
      - Multiband FCC high attenuation & CEN-B (FCC + CENELEC-B; main branch + auxiliary branch)
      - Multiband FCC high attenuation & CEN-B (CENELEC-B only; auxiliary branch)
      - Multiband single-branch FCC & CEN-A (FCC + CENELEC-A; main branch)
      - Multiband single-branch FCC & CEN-A (FCC only; main branch)
      - Multiband single-branch FCC & CEN-A (CENELEC-A only; main branch)
    - PL360:
      - PLCOUP007 (CENELEC-A only; single branch; external driver)
      - PLCOUP014 (CENELEC-B only; external driver)
      - PLCOUP012 (CENELEC-B only; single branch; internal driver)
      - PLCOUP006 (FCC only; double branch; external driver)
      - PLCOUP011 (FCC + CENELEC-A; double branch; external driver)
      - PLCOUP011 (FCC only; single branch; external driver)
  - Default G3-PLC Band:
    - In case of Multiband PLC Coupling, this option selects the G3-PLC PHY band used by default

## NVIC Configurations (Interrupt Priorities)

- The G3 MAC RT driver has a strong dependency with a delay function implemented in the HAL module. This delay function is called from the interrupt handler associated with the External Interrupt pin.
- In the Microchip implementation, the delay function uses the Time system service, which uses a timer peripheral. The timer interrupt priority must be higher (lower value) than the interrupt priority associated with the External Interrupt pin in order to ensure the correct operation.
- For MCUs that does not have DMA (for example, PIC32CXMT), the SPI interrupt priority must be higher (lower value) than the interrupt priority associated with the External Interrupt pin in order to ensure the correct operation.

## SPI Peripheral Configuration

For correct operation it is important that the SPI is properly configured in MCC. If the used peripheral supports multiple chip select lines, the corresponding NPCS has to be enabled and configured.

When SPI dependency of G3 MAC RT driver is connected to a peripheral with SPI capability, some SPI options are automatically configured. The SPI clock frequency is configured to 8 MHz by default. There is not any requirement in terms of low SPI baudrate, the user can reduce it if needed. However, it is recommended to configure it as high as possible because the lower the SPI baudrate, the slower the response time. The other SPI configuration options should not be changed.

The following figure shows an example of valid SPI configuration for a PIC32CXMT device.

Figure 1-32.SPI Configuration Options for G3 MAC RT Driver

Rev: G