16.3.1 All Macros

16.3.1.1 AND2

2-Input AND.
Figure 16-168. AND2
Table 16-351. AND2 I/O
Inputs Output
A, B Y
Table 16-352. AND2 Truth Table
A B Y
X 0 0
0 X 0
1 1 1

16.3.1.2 AND3

3-Input AND.
Figure 16-169. AND3
Table 16-353. AND3 I/O
Input Output
A, B, C Y
Table 16-354. AND3 Truth Table
A B C Y
X X 0 0
X 0 X 0
0 X X 0
1 1 1 1

16.3.1.3 AND4

4-Input AND.
Figure 16-170. AND4
Table 16-355. AND4 I/O
Input Output
A, B, C, D Y
Table 16-356. AND4 Truth Table
A B C D Y
X X X 0 0
X X 0 X 0
X 0 X X 0
0 X X X 0
1 1 1 1 1

16.3.1.4 CFG1/2/3/4 and Look-Up Tables (LUTs)

CFG1, CFG2, CFG3, and CFG4 are post-layout LUTs that implement any 1-input, 2-input, 3-input, and 4-input combinational logic functions respectively. Each of the CFG1/2/3/4 macros has an INIT string parameter that determines the logic functions of the macro. The output Y is dependent on the INIT string parameter and the values of the inputs.

16.3.1.5 CFG2

Post-layout macro implements any 2-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A and B. The INIT string parameter is 4 bits wide.
Figure 16-171. CFG2
Table 16-357. CFG2 I/O
Input Output
A,B Y = f (INIT, A, B)
Table 16-358. CFG2 INIT String Interpretation
BA Y
00 INIT[0]
01 INIT[1]
10 INIT[2]
11 INIT[3]

16.3.1.6 CFG3

Post-layout macro used to implement any 3-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A, B, and C. The INIT string parameter is 8 bits wide.
Figure 16-172. CFG3
Table 16-359. CFG3 I/O
Input Output
A, B, C Y = f (INIT, A,B, C)
Table 16-360. CFG3 INIT String Interpretation
CBA Y
000 INIT[0]
001 INIT[1]
010 INIT[2]
011 INIT[3]
100 INIT[4]
101 INIT[5]
110 INIT[6]
111 INIT[7]

16.3.1.7 CFG4

Post-layout macro used to implement any 4-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A, B, C, and D. The INIT string parameter is 16 bits wide.
Figure 16-173. CFG4
Table 16-361. CFG4 I/O
Input Output
A, B, C, D Y = f (INIT, A,B, C, D)
Table 16-362. CFG4 Truth Table
DCBA Y
0000 INIT[0]
0001 INIT[1]
0010 INIT[2]
0011 INIT[3]
0100 INIT[4]
0101 INIT[5]
0110 INIT[6]
0111 INIT[7]
1000 INIT[8]
1001 INIT[9]
1010 INIT[10]
1011 INIT[11]
1100 INIT[12]
1101 INIT[13]
1110 INIT[14]
1111 INIT[15]

16.3.1.8 BUFF

Buffer.

Figure 16-174. BUFF
Table 16-363. BUFF
Input Output
A Y
Table 16-364. Truth Table
A Y
0 0
1 1

16.3.1.9 BUFD

Buffer.
Note: The compile optimization does not remove this macro.
Figure 16-175. BUFD
Table 16-365. BUFD I/O
Input Output
A Y
Table 16-366. BUFD Truth Table
A Y
0 0
1 1

16.3.1.10 BUFD_DELAY

Buffer. The cell delay of BUFD_DELAY is about 0.4 ns at Military operating conditions. Its delay is longer than that of BUFD.
Note: Compile optimization will not remove this macro.
Figure 16-176. BUFD_DELAY
Table 16-367. BUFD_DELAY
Input Output
A Y
Table 16-368. Truth Table
A Y
0 0
1 1

16.3.1.11 CLKINT

This macro routes an internal fabric signal to the global network.
Figure 16-177. CLKINT
Table 16-369. CLKINT I/O
Input Output
A Y
Table 16-370. CLKINT Truth Table
A Y
0 0
1 1

16.3.1.12 GBR

Back-annotated macro that routes an internal fabric signal to global network.

Figure 16-178. GBR
Table 16-371. GBR
Input Output
An Y
Table 16-372. Truth Table
An Y
0 0
1 1

16.3.1.13 CLKINT_PRESERVE

This Macro routes an internal fabric signal to the global network. It has the same functionality as CLKINT except that this clock always stays on the global clock network and will not be demoted during design implementation.
Figure 16-179. CLKINT_PRESERVE
Table 16-373. CLKINT_PRESERVE I/O
Input Output
A Y
Table 16-374. CLKINT_PRESERVE Truth Table
A Y
0 0
1 1

16.3.1.14 GRESET

This Macro connects an I/O or route an internal fabric signal to the global reset network. The connection to the GRESET is hardened for radiation only if the driver is an I/O fixed at a package pin with GRESET in its function name. Routing an internal fabric signal through the GRESET macro is hardened by the radiation.

Figure 16-180. GRESET
Table 16-375. Truth Table
A Y
0 0
1 1

16.3.1.15 RCLKINT

This Macro routes an internal fabric signal to a row global buffer, thus creating a local clock.

Figure 16-181. RCLKINT
Table 16-376. RCLKINT
Input Output
A Y
Table 16-377. Truth Table
A Y
0 0
1 1

16.3.1.16 RGB

Back-annotated macro that routes an internal fabric signal to a row global buffer.

Figure 16-182. RGB.
Table 16-378. RGB
InputOutput
AnYL, YR
Table 16-379. Truth Table
AnYLYR
000
111

16.3.1.17 RGRESET

Macro used to route a triplicated fabric signal to a row global buffer and create a local reset. The three input bits must be driven by three separate logic cones replicating the paths from the source registers.

Figure 16-183. RGRESET
Table 16-380. Truth Table
A[2] A[1] A[0] Y
X 0 0 0
0 X 0 0
0 0 X 0
X 1 1 1
1 X 1 1
1 1 X 1

16.3.1.18 SLE

Sequential Logic Element.

Figure 16-184. Sequential Logic Element (SLE)
Table 16-381. Sequential Logic Element
Input Output
Name Function Name
D Data input Q
CLK Clock input
EN Active-High CLK enable
ALn Asynchronous Load. This active-low signal either sets the register or clears the register depending on the value of ADn.
ADn1 Static asynchronous load data. When ALn is active, Q goes to the complement of ADn.
SLn Synchronous load. This active-low signal either sets the register or clears the register depending on the value of SD, at the rising edge of the clock.
SD1 Static synchronous load data. When SLn is active (that is, low), Q goes to the value of SD at the rising edge of CLK.
LAT1 LAT is always tied to low. Q output is invalid when LAT=1.
Note:
  1. ADn, SD, and LAT are static signals defined at design time and need to be tied to 0 or 1.
Table 16-382. Truth Table
ALn ADn LAT CLK EN SLn SD D Qn+1
0 ADn X X X X X X !ADn
1 X 0 Not rising X X X X Qn
1 X 0 0 X X X Qn
1 X 0 1 0 SD X SD
1 X 0 1 1 X D D
X X 1 X X X X X Invalid

16.3.1.19 SLE_RT

Sequential Logic Element macro available only in post-layout netlist.

Figure 16-185. Sequential Logic Element (SLE)
Table 16-383.  Sequential Logic Element
Input Output
Name Function Q
D Data input
CLK Clock input
EN Active High CLK enable
ALn Asynchronous Load. This active low signal either sets the register or clears the register depending on the value of ADn.
ADn1 Static asynchronous load data. When ALn is active, Q goes to the complement of ADn.
SLn Synchronous load. This active low signal either sets the register or clears the register depending on the value of SD, at the rising edge of the clock.
SD1 Static synchronous load data. When SLn is active (that is, low), Q goes to the value of SD at the rising edge of CLK.
DELEN1 Enable Single-event Transient mitigation.
Note:
  1. ADn, SD, and DELEN are static signals defined at design time and need to be tied to 0 or 1.
Table 16-384. Truth Table
ALn ADn CLK EN SLn SD D Qn+1
0 ADn X X X X X !ADn
1 X Not rising X X X X Qn
1 X 0 X X X Qn
1 X 1 0 SD X SD
1 X 1 1 X D D

16.3.1.20 ARI1

The ARI1 macro is responsible for representing all arithmetic operations in the pre-layout phase.

Figure 16-186. ARI1
Table 16-385. ARI1
Input Output
A, B, C, D, FCI Y, S, FCO

The ARI1 cell has a 20 bit INIT string parameter that is used to configure its functionality. The interpretation of the 16 LSB of the INIT string is shown in the following table. F0 is the value of Y when A = 0 and F1 is the value of Y when A = 1.

Table 16-386. Interpretation of 16 LSB of the INIT String for ARI1
ADCB Y
0000 INIT[0] F0
0001 INIT[1]
0010 INIT[2]
0011 INIT[3]
0100 INIT[4]
0101 INIT[5]
0110 INIT[6]
0111 INIT[7]
1000 INIT[8] F1
1001 INIT[9]
1010 INIT[10]
1011 INIT[11]
1100 INIT[12]
1101 INIT[13]
1110 INIT[14]
1111 INIT[15]
Table 16-387. Truth Table for S
Y FCI S
0 0 0
0 1 1
1 0 1
1 1 0

ARI1 LOGIC

The 4 MSB of the INIT string controls the output of the carry bits. The carry is generated using carry propagation and generation bits, which are evaluated according to the following tables.

Table 16-388. ARI1 INIT[17:16] String Interpretation
INIT[17] INIT[16] G
0 0 0
0 1 F0
1 0 1
1 1 F1
Table 16-389. ARI1 INIT[19:18] String Interpretation
INIT[19] INIT[18] P
0 0 0
0 1 Y
1 X 1
Table 16-390. FCO Truth Table
P G FCI FCO
0 G X G
1 X FCI FCI

16.3.1.21 ARI1_CC

The ARI1_CC macro is responsible for representing all arithmetic operations in the post-layout phase. It performs all the functions of the ARI1 macro except that it does not generate the Final Carry Out (FCO).
Note: FC1 and FC0 do not perform any functionalities.
Figure 16-187. ARI1_CC
Table 16-391. ARI1_CC
Input Output
A, B, C, D, CC Y, S, P, UB

The ARI1_CC cell has a 20-bit INIT string parameter that is used to configure its functionality. The interpretation of the 16 LSB of the INIT string is shown in the following table. F0 is the value of Y when A = 0 and F1 is the value of Y when A = 1. The following table shows the interpretation of 16 LSB of the INIT string for AR1_CC.

Table 16-392. Interpretation of 16 LSB of the INIT String for AR1_CC
ADCB Y
0000 INIT[0] F0
0001 INIT[1]
0010 INIT[2]
0011 INIT[3]
0100 INIT[4]
0101 INIT[5]
0110 INIT[6]
0111 INIT[7]
1000 INIT[8] F1
1001 INIT[9]
1010 INIT[10]
1011 INIT[11]
1100 INIT[12]
1101 INIT[13]
1110 INIT[14]
1111 INIT[15]

The 4 MSB of the INIT string controls the output of the carry bits. The carry is generated using carry propagation and generation bits, which are evaluated according to the following tables.

Table 16-393. ARI1_CC INIT[17:16] String Interpretation
INIT[17] INIT[16] UB
0 0 1
0 1 !F0
1 0 0
1 1 !F1
Table 16-394. ARI1_CC INIT[19:18] String Interpretation
INIT[19] INIT[18] P
0 0 0
0 1 Y
1 X 1

The equation of S is given by:

S=Y^CC

16.3.1.22 CC_CONFIG

The CC_CONFIG macro is responsible for generating the Carry bit for each ARI1_CC cell in the cluster.

Figure 16-188. CC_CONFIG
Table 16-395. CC_CONFIG
Input Output
CI, P, UB CO, CC

CI and CO are the carry-in and carry-out, respectively, to the cell. The intermediate carry-bits are given by CC[11:0]. The functionality of the CC_CONFIG is basically evaluating CC using

CC[n] = !Px!UB+PxCC[n-1]

where CC[-1] is CI and CC[12] is CO.

Inside every cluster, there are 12 ARI1_CC cells and only one CC_CONFIG cell. The CC_CONFIG takes as input the P and UB outputs of each ARI1_CC cell in the cluster and generated the CC (carry-out bit), which is then fed to the next ARI1_CC cell in the cluster as the carry-in.

16.3.1.23 FCEND_BUFF

Buffer, driven by the FCO pin of the last macro in the Carry-Chain.

Figure 16-189. FCEND_BUFF
Table 16-396. FCEND_BUFF
InputOutput
AY
Table 16-397. Truth Table
AY
00
11

16.3.1.23.1 FCINT_BUFF

Name special Buffer, used to initialize the FCI pin of the first macro in the Carry-Chain.
Figure 16-190. FCINT_BUFF.
Table 16-398. FCINT_BUFF

Input

Output

A

Y

Table 16-399. Truth Table
A Y
0 0
1 1

16.3.1.24 RCOSC_50MHZ

The RCOSC_50MHZ oscillator is an RC oscillator that provides a free-running clock of 50 MHz at CLKOUT.

Figure 16-191. RCOSC_50MHZ

16.3.1.26 SYSRESET

It is a special-purpose macro. The Output POWER_ON_RESET_N goes low at power-up and when DEVRST_N goes low.

Figure 16-192. SYSRESET
Table 16-400. SYSRESET
Input Output
DEVRST_N POWER_ON_RESET_N
Table 16-401. Truth Table
DEVRST_N POWER_ON_RESET_N
0 0
1 1

16.3.1.27 SYSCTRL_RESET_STATUS

This is a special-purpose macro that checks the status of the System Controller. The output port RESET_STATUS goes high, if the System Controller is in reset. This macro is enabled by selecting the Enable System Controller Suspend Mode option in the Configure Programming Bitstream Settings tool within Libero. After programming, the device will enter System Controller Suspend Mode, if TRSTB is tied low during device power-up.
Note: This macro is not supported in simulation.
Figure 16-193. SYSCTRL_RESET_STATUS

16.3.1.28 DFN1

D-Type Flip-Flop.
Figure 16-194. DFN1
Table 16-402. DFN1 I/O
Input Output
D, CLK Q
Table 16-403. DFN1 Truth Table
CLK D Qn+1
not Rising X Qn
D D

16.3.1.29 DFN1C0

D-Type Flip-Flop with active-low Clear.
Figure 16-195. DFN1C0
Table 16-404. DFN1C0 I/O
Input Output
D, CLK, CLR Q
Table 16-405. DFN1C0 Truth Table
CLR CLK D Qn+1
0 X X 0
1 not Rising X Qn
1 D D

16.3.1.30 DFN1E1

D-Type Flip-Flop with active high Enable.
Figure 16-196. DFN1E1
Table 16-406. DFN1E1 I/O
Input Output
D, E, CLK Q
Table 16-407. DFN1E1 Truth Table
E CLK D Qn+1
0 X X Qn
1 not Rising X Qn
1 D D

16.3.1.31 DFN1E1C0

D-Type Flip-Flop, with active-high Enable and active-low Clear.
Figure 16-197. DFN1E1C0
Table 16-408. DFN1E1C0 I/O
Input Output
CLR, D, E, CLK Q
Table 16-409. DFN1E1C0 Truth Table
CLR E CLK D Qn+1
0 X X X 0
1 0 X X Qn
1 1 not Rising X Qn
1 1 D D

16.3.1.32 DFN1E1P0

D-Type Flip-Flop with active-high Enable and active-low Preset.

Figure 16-198. DFN1E1P0
Table 16-410. DFN1E1P0
Input Output
D, E, PRE, CLK Q
Table 16-411. Truth Table
PRE E CLK D Qn+1
0 X X X 1
1 0 X X Qn
1 1 not Rising X Qn
1 1 D D

16.3.1.33 DFN1P0

D-Type Flip-Flop with active-Low Preset.
Figure 16-199. DFN1P0
Table 16-412. DFN1P0 I/O
Input Output
D, PRE, CLK Q
Table 16-413. DFN1P0 Truth Table
PRE CLK D Qn+1
0 X X 1
1 not Rising X Qn
1 D D