16.3.3 IO1

16.3.3.1 BIBUF

Bidirectional Buffer.

Figure 16-218. BIBUF
Table 16-449. BIBUF
Input Output
D, E, PAD PAD, Y
Table 16-450. Truth Table
MODE E D PAD Y
OUTPUT 1 D D D
INPUT 0 X Z X
INPUT 0 X PAD PAD

16.3.3.2 BIBUF_DIFF

Bidirectional Buffer, Differential I/O.

Figure 16-219. BIBUF_DIFF
Table 16-451. BIBUF_DIFF
Input Output
D, E, PADP, PADN PADP, PADN, Y
Table 16-452. Truth Table
MODE E D PADP PADN Y
OUTPUT 1 0 0 1 0
OUTPUT 1 1 1 0 1
INPUT 0 X Z Z X
INPUT 0 X 0 0 X
INPUT 0 X 1 1 X
INPUT 0 X 0 1 0
INPUT 0 X 1 0 1

16.3.3.3 CLKBIBUF

Bidirectional Buffer with Input to global network.

Figure 16-220. CLKBIBUF
Table 16-453. CLKBIBUF
Input Output
D, E, PAD PAD, Y
Table 16-454. Truth Table
D E PAD Y
X 0 Z X
X 0 0 0
X 0 1 1
0 1 0 0
1 1 1 1

16.3.3.4 CLKBUF

Input Buffer to global network.

Figure 16-221. CLKBUF
Table 16-455. CLKBUF
Input Output
PAD Y
Table 16-456. Truth Table
PAD Y
0 0
1 1

16.3.3.5 CLKBUF_DIFF

Differential I/O macro to global network, Differential I/O.

Figure 16-222. INBUF_DIFF
Table 16-457. INBUF_DIFF
Input Output
PADP, PADN Y
Table 16-458. Truth Table
PADP PADN Y
Z Z Y
0 0 X
1 1 X
0 1 0
1 0 1

16.3.3.6 INBUF

Input Buffer.

Figure 16-223. INBUF
Table 16-459. INBUF
Input Output
PAD Y
Table 16-460. Truth Table
PAD Y
Z X
0 0
1 1

16.3.3.7 INBUF_DIFF

Input Buffer, Differential I/O.

Figure 16-224. INBUF_DIFF
Table 16-461. INBUF_DIFF
Input Output
PADP, PADN Y
Table 16-462. Truth Table
PADP PADN Y
Z Z X
0 0 X
1 1 X
0 1 0
1 0 1

16.3.3.8 IOINFF_BYPASS

The I/O input bypass macro is available in post-layout netlist only.

Figure 16-225. IOINFF_BYPASS
Table 16-463. IOINFF_BYPASS
Input Output
A Y
Table 16-464. Truth Table
A Y
0 0
1 1

16.3.3.9 IOENFF_BYPASS

The I/O enable bypass macro is available in post-layout netlist only.

Figure 16-226. IOENFF_BYPASS
Table 16-465. IOENFF_BYPASS
Input Output
A Y
Table 16-466. Truth Table
A Y
0 0
1 1

16.3.3.10 IOOUTFF_BYPASS

The I/O output bypass macro is available in post-layout netlist only.

Figure 16-227. IOOUTFF_BYPASS
Table 16-467. IOOUTFF_BYPASS
Input Output
A Y
Table 16-468. Truth Table
A Y
0 0
1 1

16.3.3.11 IOPAD_BI

The I/O output bypass macro is available in post-layout netlist only.

Figure 16-228. IOPAD_BI
Table 16-469. IOPAD_BI
Input Output
D, E, PAD PAD, Y, Y_HW
Table 16-470. Truth Table
MODE E D PAD Y Y_HW
OUTPUT 1 D D D D
INPUT 0 X Z X X
INPUT 0 X PAD PAD PAD

16.3.3.12 IOPADP_BI

The I/O PAD bi-directional macro is available in post-layout netlist only.

Figure 16-229. IOPADP_BI
Table 16-471. IOPADP_BI
Input Output
N2PIN_P, OIN_P, EIN_P, PAD_P PAD_P, IOUT_P, IOUT_HW_P
Table 16-472. Truth Table
MODE EIN_P OIN_P PAD_P N2PIN_P IOUT_P OUT_HW_P
OUTPUT 1 0 0 1 0 0
OUTPUT 1 1 1 0 1 1
INPUT 0 X Z Z X X
INPUT 0 X 0 0 X X
INPUT 0 X 1 1 X X
INPUT 0 X 0 1 0 0
INPUT 0 X 1 0 1 1

16.3.3.13 IOPADN_BI

The I/O PAD bi-directional macro is available in post-layout netlist only.

Figure 16-230. IOPADN_BI
Table 16-473. IOPADN_BI
Input Output
OIN_P, EIN_P, PAD_P PAD_P, N2POUT_P
Table 16-474. Truth Table
MODE EIN_P OIN_P PAD_P N2POUT_P
OUTPUT 1 1 0 0
OUTPUT 1 0 1 1
INPUT 0 X Z X
INPUT 0 X 0 X
INPUT 0 X 1 X
INPUT 0 X 0 0
INPUT 0 X 1 1

16.3.3.14 IOPADP_IN

The I/O PAD input macro is available in post-layout netlist only.

Figure 16-231. IOPADP_IN
Table 16-475. IOPADP_IN
Input Output
PAD_P, N2PIN_P IOUT_P, IOUT_HW_P
Table 16-476. Truth Table
PAD_P N2PIN_P IOUT_P IOUT_HW_P
Z X X X
0 X 0 0
1 X 1 1

16.3.3.15 IOPADN_IN

The I/O PAD input macro is available in post-layout netlist only.

Figure 16-232. IOPADN_IN
Table 16-477. IOPADN_IN
Input Output
PAD_P N2POUT_P
Table 16-478. Truth Table
PAD_P N2POUT_P
0 1
1 0

16.3.3.16 IOPADP_TRI

The I/O PAD tristate output macro is available in post-layout netlist only.

Figure 16-233. IOPADP_TRI
Table 16-479. IOPADP_TRI
Input Output
OIN_P, EIN_P PAD_P
Table 16-480. Truth Table
OIN_P EIN_P PAD_P
X 0 Z
OIN_P 1 OIN_P

16.3.3.17 IOPADN_TRI

The I/O PAD tristate output macro is available in post-layout netlist only.

Figure 16-234. IOPADN_TRI
Table 16-481. IOPADN_TRI
Input Output
OIN_P, EIN_P PAD_P
Table 16-482. Truth Table
OIN_P EIN_P PAD_P
X 0 Z
0 1 1
1 1 0

16.3.3.18 IO_DIFF

The I/O Differential macro is available only in post-layout netlist (place holder to reserve the N location).

Figure 16-235. IO_DIFF

Input = YIN

16.3.3.19 IOTRI_OB_EB

The I/O feed through macro is available in post-layout netlist only.

Figure 16-236. IOTRI_OB_EB
Table 16-483. IOTRI_OB_EB
Input Output
D, E DOUT, EOUT
Table 16-484. Truth Table
D DOUT
0 0
1 1
Table 16-485. Truth Table
E EOUT
0 0
1 1

16.3.3.20 IOBI_IB_OB_EB

The I/O feed through macro is available in post-layout netlist only.

Figure 16-237. IOBI_IB_OB_EB
Table 16-486. IOBI_IB_OB_EB
Input Output
D, E, YIN DOUT, EOUT, Y
Table 16-487. Truth Table
D DOUT
0 0
1 1
Table 16-488. Truth Table
E EOUT
0 0
1 1
Table 16-489. Truth Table
YIN Y
0 0
1 1

16.3.3.21 OUTBUF

Output buffer.

Figure 16-238. OUTBUF
Table 16-490. OUTBUF
Input Output
D PAD
Table 16-491. Truth Table
D PAD
0 0
1 1

16.3.3.22 OUTBUF_DIFF

Output buffer, Differential I/O.

Figure 16-239. OUTBUF_DIFF
Table 16-492. OUTBUF_DIFF
Input Output
D PADP, PADN
Table 16-493. Truth Table
D PADP PADN
0 0 1
1 1 0

16.3.3.23 TRIBUFF

Tristate output buffer.

Figure 16-240. TRIBUFF
Table 16-494. TRIBUFF
Input Output
D, E PAD
Table 16-495. Truth Table
D E PAD
X 0 Z
D 1 D

16.3.3.24 TRIBUFF_DIFF

Tristate output buffer, Differential I/O.

Figure 16-241. TRIBUFF_DIFF
Table 16-496. TRIBUFF_DIFF
Input Output
D, E PADP, PADN
Table 16-497. Truth Table
D E PADP PADN
X 0 Z Z
0 1 0 1
1 1 1 0

16.3.3.25 DDR_IN

The DDR_IN macro is available for both pre-layout and post-layout simulation flows. It consists of two SLE macros and a latch. The input D must be connected to an I/O.

Figure 16-242. DDR_IN
Table 16-498. DDR_IN
InputOutput
NameFunctionName
DData inputQR

QF

CLKClock input
ENActive High CLK enable
ALnAsynchronous load. This active low signal either sets the register or clears the register depending on the value of ADn.
ADn1Static asynchronous load data. When ALn is active, QR and QF go to the complement of ADn.
SLnSynchronous load. This active low signal either sets the register or clears the register depending on the value of SD, at the rising edge of CLK.
SD1Static synchronous load data. When SLn is active (that is, low), QR and QF go to the value of SD at the rising edge of CLK.
Note:
  1. ADn and SD are static inputs defined at design time and need to be tied to 0 or 1.
Table 16-499. Truth Table
ALnCLKENSLndfn+1 (Internal Signal)QRn+1QFn+1
0XXX!ADn!ADn!ADn
1Not risingXXdfnQRnQFn
10XdfnQRnQFn
110dfnSDSD
111dfnDdfn
1XXDQRnQFn

16.3.3.26 DDR_OUT

The DDR_OUT macro is an output DDR cell and is available for pre-layout simulation. It consists of two SLE macros. The output Q must be connected to an I/O.

Figure 16-243. DDR_OUT
Table 16-500. DDR_OUT
Input Output
Name Function
DR Data input (Rising Edge) Q
DF Data input (Falling Edge)
CLK Clock input
EN Active High CLK enable
ALn Asynchronous load. This active low signal either sets the register or clears the register depending on the value of ADn.
ADn1 Static asynchronous load data. When ALn is active, Q goes to the complement of ADn.
SLn Synchronous load. This active low signal either sets the register or clears the register depending on the value of SD, at the rising edge of CLK.
SD1 Static synchronous load data. When SLn is active (that is, low), Q goes to the value of SD at the rising edge of CLK.
Note:
  1. ADn and SD are static inputs defined at design time and need to be tied to 0 or 1.
Table 16-501. Truth Table
ALn CLK EN SLn QRn+1 QFn+1 Qn+1
0 X X X !ADn !ADn !ADn
1 1 X X QRn QFn QRn
1 0 X QRn QFn QRn+1
1 1 0 SD SD QRn+1
1 1 1 DR DF QRn+1
1 0 X X QRn QFn QFn

16.3.3.27 DDR_OE_UNIT

The DDR_OE_UNIT macro is an output DDR cell that is only available for post-layout simulations. Every DDR_OUT instance is replaced by DDR_OE_UNIT during compile. The DDR_OE_UNIT macro consists of a DDR_OUT macro with inverted data inputs and SDR control.

Figure 16-244. DDR_OE_UNIT
Table 16-502. DDR_OE_UNIT
Input Output
Name Function
DRn Data input (Rising Edge) Q
DFn Data input (Falling Edge)
CLK Clock input
EN Active High CLK enable
ALn Asynchronous load. This active low signal either sets the register or clears the register depending on the value of ADn.
ADn Static asynchronous load data. When ALn is active, Q goes to the complement of ADn.
SLn Synchronous load. This active low signal either sets the register or clears the register depending on the value of SD, at the rising edge of CLK.
SD Static synchronous load data. When SLn is active (that is, low), Q goes to the value of SD at the rising edge of CLK.
SDR Controls whether the cell operates in DDR (SDR = 0) or SDR (SDR = 1) modes.
Table 16-503. Truth Table
SDR ALn CLK EN SLn QRn+1 QFn+1 Qn+1
0 0 X X X !ADn !ADn !ADn
0 1 1 X X QRn QFn QRn
0 1 0 X QRn QFn QRn+1
0 1 1 0 SD SD QRn+1
0 1 1 1 !DRn !DFn QRn+1
0 1 0 X X QRn QFn QFn

16.3.3.28 IOIN_IB

Buffer macro available in post-layout netlist only.

Figure 16-245. IOIN_IB
Table 16-504. IOIN_IB
Input Output
YIN, E Y
Note: E input is not used.
Table 16-505. Truth Table
YIN Y
Z X
0 0
1 1

16.3.3.29 IOPAD_IN

Input I/O macro available in post-layout netlist only.

Figure 16-246. IOPAD_IN
Table 16-506. IOPAD_IN
Input Output
PAD Y, Y_HW
Table 16-507. Truth Table
PAD Y, Y_HW
Z X
0 0
1 1

16.3.3.30 IOPAD_TRI

Tri-state output buffer available in post-layout netlist only.

Figure 16-247. IOPAD_TRI
Table 16-508. IOPAD_TRI
Input Output
D, E PAD
Table 16-509. Truth Table
D E PAD
X 0 Z
0 1 0
1 1 1

16.3.3.31 IOINFF

Registered input I/O macro available only in post-layout netlist.

Figure 16-248. IOINFF
Table 16-510. IOINFF
Input Output
Name Function Q
D Data
CLK Clock
EN Enable
ALn Asynchronous Load (Active-Low)
ADn1 Asynchronous Data (Active-Low)
SLn Synchronous Load (Active-Low)
SD1 Synchronous Data
DELEN1 Enable Single-event Transient mitigation
Note:
  1. ADn, SD, and DELEN are static signals defined at design time and need to be tied to 0 or 1.
Table 16-511. Truth Table
ALn ADn CLK EN SLn SD D Qn+1
0 ADn X X X X X !ADn
1 X Not rising X X X X Qn
1 X 0 X X X Qn
1 X 1 0 SD X SD
1 X 1 1 X D D

16.3.3.32 IOOEFF

Registered output I/O macro available only in post-layout netlist. The IOOEFF is an SLE_RT with an inverted data input.

Figure 16-249. IOOEFF
Table 16-512. IOOEFF
Input Output
Name Function Q
D Data
CLK Clock
EN Enable
ALn Asynchronous Load (Active Low)
ADn1 Asynchronous Data (Active Low)
SLn Synchronous Load (Active Low)
SD1 Synchronous Data
DELEN1 Enable Single-event Transient mitigation
Note:
  1. ADn, SD, and DELEN are static signals defined at design time and need to be tied to 0 or 1.
Table 16-513. Truth Table
ALn ADn CLK EN SLn SD D Qn+1
0 ADn X X X X X !ADn
1 X Not rising X X X X Qn
1 X 0 X X X Qn
1 X 1 0 SD X SD
1 X 1 1 X D !D