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# 10.6 Migrating Designs to Libero SoC 2022.1

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## 10.6.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2022.1. For more information about updating a core version, see section Updating a Core Version.

Table 10-1.Core Enhancements and Upgrades
Core | 2022.1 Version | Status | Comments
--- | --- | --- | ---
PF_DDR3 | 2.4.117 | Production | Changed the minimum value of Memory Clock Frequency from 0 MHz to 400 MHz. Made DM and ECC s mutually exclusive selections.
PF_DDR4 | 2.5.105 | Production | Changed the minimum value of Memory Clock Frequency from 0 MHz to 400 MHz. Made DM and ECC mutually exclusive selections.
PF_INIT_MONITOR | 2.0.302 | Production | See section INIT MONITOR Enhancement to Latch Outputs when Using System Controller Suspend Mode for details.
PF_IOD_CDR_CCC | 2.1.107 | Production | Fixed internal I/O parameters after formal characterization of the device.
PF_LPDDR3 | 2.3.114 | Production | Changed the minimum value of Memory Clock Frequency from 0 MHz to 400 MHz.
PF_PCIE | 2.0.116 | Production | See section PCIe Root-port Capability to Work with APB Initiator to Control the PERSTn Output to Downstream PCIe Endpoints for details.
PFSOC_INIT_MONITOR | 1.0.302 | Pre-Production | See section INIT MONITOR Enhancement to Latch Outputs when Using System Controller Suspend Mode for details.
RTG4FCCC | 2.0.203 | Production | Updated the parameter type of `VCOFREQUENCY`.

## 10.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download and upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Update Component Version. The component will be regenerated automatically.
   Note: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version downloads automatically from the Update Component Version dialog if needed.
2. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right click on the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance and connect them or tie them off as needed, and regenerate the SmartDesign component.
3. Build the Design Hierarchy and derive the Timing Constraints again using the Constraint Manager tool to use the latest generated core timing constraints.
4. Rerun the design flow.

Rev: 2026.1

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