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# 6.2 Changes that Address Important Issues

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Libero SoC v2023.2 includes changes that address certain important issues.

## 6.2.1 PolarFire FPGA , PolarFire SoC, and RT PolarFire FPGA

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### 6.2.1.1 Programmable I/O Delay Update on Ports Using Combined I/O Registers

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I/Os in PolarFire, PolarFire SoC, and RT PolarFire technology could program certain additional delays on their input, output or output-enable paths determined either automatically through Repair min-delay violations or by users through the I/O Editor or I/O PDC constraint file. Each I/O path could also be combined with a directly connected flip-flop in the design to form an instance of IOREG either automatically through timing-driven Place and Route or through a user directive in the NDC constraint file.

Prior to Libero SoC v2023.2, any programmable delay in the path of a combined IOREG would get disabled. Libero SoC v2023.2 fixes this issue.

### 6.2.1.2 PF_IOD: OCTAL_PHY Update

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Starting from Libero SoC v2023.2, designs that previously instantiated the PF_IOD_OCTAL PHY v2.0.106 with Differential DQS enabled will be invalidated to the pre-synthesis design state. Please note that the Differential DQS option was introduced in Libero SoC v2021.3.

To resolve a necessary missing connection from IOPADP_BI to the LANECTRL: DQS pin, designs using PF_IOD_OCTAL_DDR v2.0.106 with Differential DQS enabled must upgrade to Libero SoC v2023.2 and re-run the design flow from Synthesis onwards.

Additionally, the PF_IOD_OCTAL_DDR core has been updated to version v2.0.108 with Libero SoC v2023.2. This update addresses non-blocking code assignments that were encountered in a combinational block. There are no functional changes.

### 6.2.1.3 USK, Authenticated Plain Text, and Authenticated Cipher Text Clients

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USK, Authenticated Plain Text, and Authenticated Cipher Text clients are available only for data security-enabled PolarFire and RT PolarFire devices. Authenticated and non-Authenticated Cyphertext clients can no longer be added in non-S devices for PolarFire, RT PolarFire, and PolarFire SoC. The flow errors-out if users try to configure these clients using Tcl scripts. The design flow will be invalidated when opening an older project that has Authenticated and non-Authenticated Cyphertext clients configured for non-S devices. Previous Libero versions incorrectly provided users with access to these features.

## 6.2.2 PolarFire FPGA and PolarFire SoC

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### 6.2.2.1 MPF050T/TS/TL/TLS, MPFS025T/TS/TL/TLS: High-Speed I/O Clock Connectivity Update

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Prior to Libero SoC v2023.2, designs for MPF050T/TS/TL/TLS or MPFS025T/TS/TL/TLS devices could have placed HS_IO_CLK instances at infeasible locations. Libero SoC v2023.2 fixes this issue.

## 6.2.3 PolarFire SoC

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### 6.2.3.1 MPFS460T/TS/TL/TLS: Timing of CDR Paths

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Libero SoC v2023.2 contains timing updates for CDR application designs targeting MPFS460T/TS/TL/TLS devices.

## 6.2.4 PolarFire FPGA

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### 6.2.4.1 PolarFire MPF200T FCVG484: I/O Banks 4 and 5 VDDI DRC, Design Invalidation

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I/O banks 4 and 5 on the FCVG484 package of MPF200T/TS/TL/TLS devices are connected to a single VDDI supply. Prior to Libero SoC v2023.2, users could have assigned different voltages to the two banks in a design. Users would observe the discrepancy during board layout, as the pin report contains a single supply for both the banks. Libero SoC v2023.2 enforces a design rule check (DRC) on the VDDI assignments to the two banks.

## 6.2.5 RTG4

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### 6.2.5.1 RTG4 CCC Improvements

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#### RTG4FCCC and RTG4FCCCECALIB

The generated clock constraints for CCC PLL configured in external feedback mode with dedicated input now use `-pll_feedback` and `-pll_output`. Users must use the `set_external_delay` constraint to specify the delay outside the FPGA to complete the feedback loop. For more information about the `set_external_delay` constraint, see the Timing Constraints Editor User Guide .

In addition, the accuracy has been improved for PLL solutions in PLL-internal feedback or when output resynchronization is disabled.

#### RTG4FCCCECALIB

The RTG4FCCCECALIB core was updated to remove the dependency on PLL lock for the GLx outputs that bypass the PLL output. Previously, using an RTG4FCCCECALIB core v2.2.007 or earlier bundled with Libero SoC v2023.1 or earlier, with the following configuration options enabled, caused a logical error in the generated core that prevented any clock outputs from the CCC:

- The PLL option for Output Resynchronization After Lock was set to hold outputs LOW until LOCK (this is not the default setting).
- One of the CCC GLx outputs sourced the 50MHz clock from the internal RC_OSC primitive macro, which was then wrapped around to clock the CLK_50MHZ RTG4FCCCECALIB input pin.
- The CCC GLx output sourcing the 50MHz RC_OSC clock was set to expose the GLx_Yx_ARST_N and GLx_Yx_EN input signals to the user design.

In this scenario, the GLx output sourced from the internal 50MHz RC_OSC clock does not depend on the PLL lock assertion and, as a result, the output should not be gated by the PLL lock signal, regardless of the Output Resynchronization After Lock setting for the other CCC outputs that do depend on the PLL output. By gating off the clock sourcing the CLK_50MHZ, it prevented the PLL calibration state machine from running, and, consequently, the RTG4FCCCECALIB core using the configuration above would not output any clocks nor lock onto the PLL reference clock. To avoid this scenario, update to the latest version of the RTG4FCCCECALIB core.

Rev: 2026.1

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