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# 10.2 Changes that Address Important Issues

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## 10.2.1 PolarFire, RT PolarFire, and PolarFire SoC

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This section includes changes that address certain important issues related to the PolarFire, RT PolarFire, and PolarFire SoC family devices.

### 10.2.1.1 New Timing Constraint Flow to Automatically Account for Global Clock Jitter

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Libero SoC v2022.1 introduces the automatic computation of system clock jitter for Place & Route and Timing analysis. With this feature, you need specify only the clock jitter of any FPGA primary inputs using the `set_input_jitter` constraint.

The following global clocking resources are susceptible to jitter:

- Global fabric clocks nets distributed throughout the FPGA using global networks.

- External output clocks generated within the FPGA, routed through global networks, and propagated outside of the FPGA by means of HSIO or GPIO output buffers.

- Transceiver clocks generated within the FPGA and routed to/from Transceiver TX and RX through global networks.

- Other sources of jitter, such as PLL- and DLL-generated jitter.

You can add margin to the estimated jitter of a clock using the `set_clock_uncertainty` constraint. `set_system_jitter` constraint overrides the global jitter value and should be used cautiously.

System jitter is estimated based on the count of registers and RAM blocks in the synthesized netlist and the related clock domain switching frequency. A report detailing the jitter estimation is generated. Path reports include the clock jitter as an extra line item.

For more information, see the PolarFire Family Clocking Resources User Guide

### 10.2.1.2 INIT MONITOR Enhancement to Latch Outputs when Using System Controller Suspend Mode

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The `PF_INIT_MONITOR` and `PFSoC_INIT_MONITOR IP` cores have been updated to latch the IP core outputs. This is required to maintain the IP outputs when using system controller suspend mode. To enable this feature, check the option Latch System Controller Outputs in the IP configuration dialog and connect the generated core’s `CLK_FROM_RCOSC_160MHZ` input port to the internal 160 MHZ RCOSC. This updated IP core should be used by all PolarFire, RT PolarFire, and PolarFire SoC designs that use the System Controller Suspend Mode (SCSM) feature. You will be reminded by alert messages at various stages of the design flow.

    System Controller Suspend Mode is enabled. If you have not already enabled it, make sure the Initialization Monitor IP Core is configured to Latch System Controller outputs and that the internal 160 MHZ RCOSC is connected to the CLK_FROM_RCOSC_160MHZ input port.

For more information, see the PolarFire Family Power-Up and Resets User Guide .

### 10.2.1.3 PCIe L2P2 Support in Root-Port and Endpoints

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Software-driven power management states such as L2P2 in PolarFire PCIESS Root-Port and End-points are not supported. For more information, see the PolarFire Family PCI Express User Guide .

### 10.2.1.4 PCIe Root-port Capability to Work with APB Initiator to Control the PERSTn Output to Downstream PCIe Endpoints

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The PCIe register space has been updated so that when it is configured as Root-Port, the APB initiator can control/toggle the PCIe `PERSTn` output through one of the registers. For more information, see PolarFire Family PCI Express User Guide .

## 10.2.2 SmartFusion2, IGLOO2, RTG4

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This section includes changes that address certain important issues related to the SmartFusion2, IGLOO2, and RTG4 family devices.

### 10.2.2.1 DDR Memory Controller Change of Memory Density

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Implemented change of memory density from 4GB to 2GB on SmartFusion2, IGLOO2, and RTG4 FPGA device families. For FDDR and MDDR cores, based on the selected data width, row, col, bank bit widths, DRC is shown if the selected configuration will result in a memory density larger than 2GB.

For more information, see https://www.microchip.com/product-change-notifications/#/17141/ALAN-15FPNL260.

Rev: 2026.1

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