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# 5.6 Migrating Designs to Libero SoC

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## 5.6.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2023.2. For more information about updating a core version, see section Updating a Core Version.

Table 5-2.Core Enhancements and Upgrades
Core | 2023.2 Version | Status | Comments
--- | --- | --- | ---
CORESMARTBERT | 2.10.100 | Production | Repackaged with the latest PF_XCVR core version.
PF_IOD_GENERIC_TX | 2.0.117 | Production | Fixed TX clock simulation issue by assigning OE_DATA properly.
PF_IOD_OCTAL_DDR | 2.0.108 | Production | See section PF_IOD: OCTAL_PHY Update.
PF_PCIE | 2.0.121 | Production | SEC_ERROR_EVENT_CNT and DED_ERROR_EVENT_CNT register access in SmartDebug.
PF_RGMII_TO_GMII | 1.3.109 | Production | Repackaged PF_RGMII_TO_GMII with the latest PF_IOD_GENERIC_TX.
PF_SRAM_AHBL_AXI | 1.2.111 | Production | Resolved logic issue when two transactions occur consecutively, such that you read from a different slave using AHB, and subsequently attempt to write using this slave. Also, removed any unused signal.
PF_TX_PLL | 2.0.304 | Production | See section Additional XCVR Preset Settings.
PF_XCVR_ERM | 3.1.205 | Production | See section Additional XCVR Preset Settings.
RTG4FCCCECALIB | 2.2.009 | Production | See section RTG4 CCC Improvements.
RTG4_SRAM_AHBL_AXI | 1.0.119 | Production | Resolved logic issue when two transactions occur consecutively, such that you read from a different slave using AHB, and subsequently attempt to write using this slave. Also, removed any unused signal..

## 5.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right-click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

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