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# 5.4 Software Features and Enhancements

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## 5.4.1 ModelSim Pro ME and QuestaSim ME Simulator Tools Upgraded to v2023.4

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The Libero SoC v2024.1 release supports the upgraded 2023.4 versions of ModelSim Pro ME and QuestaSim ME simulation tools. This will be the final Libero SoC release with ModelSim Pro ME as the default simulator.

## 5.4.2 Synplify Pro ME and Identify ME Tools Upgraded to V-2023.09M

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The Libero SoC v2024.1 release supports V2023.09M versions of Synplify Pro ME and Identify ME tools.

The following describe the key enhancements in Synplify Pro V2023.09:

- RTG4: Enabled by default, the feature of initializing fabric registers using the initial value specified in RTL. To disable this feature:

      set_option -support_reg_init 0

  RAM and DSP registers with reset and zero initial values will be considered for packing into respective primitives.
  Attention: If RTL has address registers initialized to zero, they are not considered for inferring LSRAM primitive because doing so is functionally incorrect. In these scenarios, there will be a difference in area when register initialization is enabled/disabled. If register initialization feature is disabled, initial values on address registers are ignored, thereby facilitating RAM inference.

- An enhancement has been made to pack an Enable pin into SLE if it is an I/O register. This is done to eliminate fanout on output port to enable packing of register into I/O pads. Because of this change, timing violations in designs might be encountered where multicycle paths ending on EN pin are defined. Microchip recommends that users apply the multicycle path to encompass both D and EN using a `get_cells` command in their SDC constraint file.

- In Automatic Compile Point (ACP) synthesis, do not perform TMR on the driver and synchronizer flip flops on safe CDC path if the attribute syn_radhardlevel=tmr is applied on the top-level module or sub module.

- All registers that get TMR’ed are now reported correctly in the synthesis TMR report.

- Libero SoC v2024.1 P&R adds detection for manually designed structural TMR.

- In addition, Libero SoC v2024.1 P&R generates another TMR report (tmr_report.csv) containing all soft TMR FF triplets.

- Libero SoC v2024.1 P&R generates a CDC synchronizer report (cdc_synchronizer.csv) containing all CDC synchronizer FF pairs.

## 5.4.3 Support for Microsoft Windows 11

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Libero SoC v2024.1 introduces support for the Microsoft Windows 11 operating system.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.