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# 12.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2021.1 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 12-3.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Description | Resolution
--- | --- | ---
1129393 | Synplify Pro should generate the CDC report in .csv format. | Libero's report now shows the CDC report with column filtering and sorting capabilities.
493642-2279076374 | Tri-state arcs are missing from the BA SDF. | The missing Tri-state arcs in the BA sdf has been resolved by adding 4 delay triplets to iopath arc (`E -> PAD`). Cells affected are `IOPAD_TRI` and `IOPAD_BI`.
493642-2573858783 | `SD_CONNECT`: Canvas should pan automatically when the edge of the canvas is reached. | Fixed the issue where canvas does not automatically pan when the selection or connection tool reaches the edge of the canvas.
493642-2589545643 | The Archive Project function creates folders with the wrong creation date. | The archive function has been fixed to show the correct date and time.
493642-2600387353 | `HDL_LANGUAGE`: DH: A VHDL recursive error is reported, but the design flow is passed. | The priority of this message has been reduced from an error to a warning.
493642-2606808569 | Request to add the command `smartpower_set_thermalmode` to the Tcl Commands User Guide | Updated the Tcl Commands User Guide to include the `smartpower_set_thermalmode` command documentation.
493642-2651664363 | Absolute/relative path: `export_script` does not export the relative path for the create_hdl_core TCL command. | Libero now exports the relative path for the HDL+ component as part of the Project Export procedure.
493642-2686416398 | `SERDES_REFCLK IO` std selection using `serdes_vddi` should be more user friendly. | A tool tip has been added for the `SERDES_VDDI` rail in the RTG4 Power Estimator.
493642-2700670264 | RTG4: unused bank power missing | The I/O bank static calculation formula has been updated for all rails in the RTG4 power estimator.
493642-2707049852 | Retain the Design Initialization flow settings for different runs. | User-selected Memory initialization and Storage selection information in Fabric RAMs of Design and Memory Initialization are retained (i.e., user-selected information in Fabric RAMs are shown if the user returns to the Design Initialization tab and then goes to the Fabric RAMs tab).
493642-2736369334 | DDR IO Margin\Training Iterator: Training failure not indicated. | When checking for the `CTRLR_READY` signal and flagging it as error if it is not HIGH, the training Iterator stage shows as failed and the tooltip reads Controller Ready Not High.
493642-2736850582 | `PF_SOC`: MSS: Option to disable SD card pins `SD_WP` and `SD_POW` in the PolarFire SoC MSS configurator. | Added the Boolean parameter `Disable SD_WP` and `SD_POW` ports below the SD usage combo box. If this parameter is enabled, ports usage is disabled. Default is false.
493642-2740070097 | The Tcl script does not have a command to import memory files. | Users can specify imported memory file information when configuring IGLOO2 TPSRAM, DPSRAM, and URAM through Tcl using the parameter `IMPORT_FILE`. This parameter accepts absolute and relative paths as inputs.
493642-2743422823, 493642-2776783309 | MT25QL128 and MT25QU128ABA1EW7-0SIT SPI Flash Programming support in Libero SoC v12.4. | The SPI-Flash Programming section under Known Issues in Libero SoC v12.4 has been updated.
493642-2744828403 | Providing support for JTAG reading of data integrity bits in PolarFire. | Users can now see the Data Integrity Bits value when running the `DEVICE_INFO` action in Libero and FlashPro Express.
493642-2747892376 | Input to output timing paths in SmartTime v12.4. | Updated path tracing to report paths ending on the output port used as a clock.
493642-2748440670 | RTG4: PLL loses lock during simulationF. | The message displayed during simulations is added below the Miscellaneous Options section in the RTG4 FCCC with Enhanced PLL Calibration Configuration User Guide.
493642-2771623606 | PolarFire SPM: Enhance the SPM GUI to clarify programming and debugging restrictions. | The Disable Auto Programming and IAP Services option moved from the Disable programming interfaces group. The option behavior has not changed
493642-2781407336 | RTG4 CCC simulation with dynamic delays sometimes has a phase shift of 180 degrees. | Fixed the PLL simulation model to sync the PLL output and FB clock with input `REF CLK` when a new value of `RF_DLINE` is loaded into the `FCCC_PDLY_CR` register.
493642-2786902308 | Job: `fpga_mapper` terminates with the error status 253. | This issue has been resolved in the Synplify Pro bundled with this Libero release.
493642-2788133376 | SPI Data Storage client with Filled with 1s option is not programming the external SPI properly. | The Filled with 1s option is now supported.
493642-2794138019 | Misleading message in the log for RTG4 SEDES design. | Clarified message for the currently selected device package.
493642-2796571518 | Support for the FlashPro TCL command `enable_prg_type` support for FlashPro 5. | The command can be used to enable FlashPro 5, FlashPro 6, and embedded FlashPro 6.
493642-2798908881 | RTG4_UPROM: Issue updating RTG4 UPROM using the TCL script in Libero SoC v12.5. | The issue related to updating RTG4 UPROM contents using the TCL command `UPDATE_UPROM` has been resolved.
493642-2800897360 | NetlistViewer runs out of memory because it fails to recognize a RAM in VHDL. | The NetlistViewer issue has been resolved.
493642-2804329140 | I/O Editor crashes when clicking on a Pin group. | The I/O Editor issue has been resolved.
493642-2805303278 | SmartFusion2 simulation PLL issues. | Fixed the PLL simulation model to deassert PLL lock when the reference clock stops during the simulation.
493642-2807685157 | `BUFD_DELAY` in RTG4 is notated with big red question mark. | This issue has been resolved.
493642-2808626348 | Timing path sorting is not working in the detail view. | Updated the condition to show the correct expanded path information for the selected timing path in SmartTime tables.
493642-2809774357 | `PF_INIT_MONITOR`: Synthesis fails in Libero SoC v12.6 after updating `PF_INIT_MONITOR`. | Synthesis fails because of an undriven `AND` gate. The `AND` gate instance with undriven input pins has been removed.
493642-2811312932 | SDC processing takes too much time for customer designs. | Improved constraint checking runtime.
493642-2811320316, 493642-2819141478 | Issue exporting the firmware in Libero SoC v12.6 through TCL script. | Added the Tcl command export_firmware.
493642-2817907985 | `PF_QDR`: CoreQDR BFM simulation: X observed when reading upper addresses. | The QDR BFM simulation model has been updated to work properly at upper addresses.
493642-2817917898 | Refresh command in Tcl script unchecks SDC files for Timing Verification. | Timing constraints associated with the verify timing tool are now retained after Build Design hierarchy or Refresh option (F5) in No Synth flow.
493642-2818533273, 493642-2820758688 | SmartFusion2: Issue updating the eNVM content in Libero SoC v12.6 using the TCL script. | Issues related to updating `IGLOO2MSS_ENVM` contents using the TCL command `UPDATE_ENVM` have been resolved.
493642-2813231063 | Repair min-delay violations take a long time in Libero SoC v12.6. | The repair algorithm has been improved to optimize for congestion.
493642-2818836281 | Probe insertion changes some project settings. | This issue is fixed in this release. The device configuration settings from Libero are retained after probe insertion.
493642-2820145985 | Place and Route error occurs with fixed macro locations in Libero v12.6. | The clustering algorithm was updated to handle fixed cells with TMR separation.
493642-2821156844 | `RTG4_UPROM`: Libero deletes `UPROM.cfg`. | The `UPROM.cfg` file is no longer being deleted after re-opening an RTG4 UPROM configurator.
493642-2825769475 | SmartTime is missing the User Set. | Updated path tracing to report paths that are part of the clock network.

Table 12-4.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Description | Resolution
--- | ---
PolarFire -1 speed-grade devices limit the maximum DDR3 GPIO rate to 800 Mbps. | The maximum rate for GPIO DDR3 for PolarFire -1 devices is 1067 Mbps
PolarFire SoC Icicle embedded programmer had a longer programming time in Linux than in Windows. | PolarFire SoC Icicle embedded programmer no longer has a longer programming time in Linux than in Windows.
The PF_IOD GUI does not allow non-integer frequencies. | The Validate rules on `DATA_RATE` for both RX and TX IOD GENERIC cores have been changed to accept floating values for `DATA_RATE`.
Instantiating a tamper macro to reset a device by asserting its `RESET` input without configuring or enabling its features causes Libero to generate an error when the `.spi` file from this image is used to configure design initialization. The error message says that the golden image cannot contain security. The tamper macro has no security feature enabled (only reset input/functionality is used) and no silicon signature and customer security is enabled. Although the SPI bitstream should not contain any security components, it does. | Users can now load an SPI file as a Recovery/Golden client in the configure design initialization tool when exported from a Libero design that instantiates the tamper macro without enabling any features.
Runtime issue for RTG4: Compile takes approximately 2 hours to complete. | Fixed algorithm to reduce runtime for this corner case.
SPI Flash init configuration and golden image with tamper macro. | The security component is not added to the bitstream if no tamper macro settings are selected. This allows the bitstream to load as a golden client.
RTG4 Global net report fanout is incorrect. | The value of the Fanout column has been corrected to show the real fanout of the net.
Construct does not allow loading of SPI Flash file automatically. | In FlashPro Express, users can now load a SPI Flash file for PolarFire and PolarFire SoC devices after creating a new job project by constructing a JTAG chain automatically.
The `PF_XCVR_REF_CLK GLOBAL` path to Fabric logic is missing. | Libero now enables the path from the XCVR Ref Clk to the Fabric.
`PF_DDR_OCTAL`: Add individual tap adjustments for multiple memory chips. | See New Post-layout Editing of I/O Attributes and Delay Parameters.
I/O registers assigned with PF_IO macro are not reported. | Compile, Pin, and IOFF reports for G5 have been updated to display I/O registers assigned with the PF_IO macro.
The SmartPower VCD + Vectorless: large frequency value is annotated after import. | The SmartPower code now annotates pin toggle rates using the correct clock domain for this corner case.
Clock and logic frequency are limited to 300 MHz. | Power estimator has been revised to allow frequencies up to 425 MHz to be specified in the Clock and Logic tabs.
Although `PCIE K_BRIDGE_SPEED` is not locked, if it had a value of 1 for `PCIE#_CONFIG_PCIE_#_K_BRIDGE_SPEED_LOCK`, it was reported as an error. | This issue has been resolved and is no longer reported as an error.
Internal Error/RTG4:Libero crashes when trying to modify Op Cond on 3.3v.. assertion at OperatingCondition.cpp", line 458. | Changing the temperature range, core voltage range, or default I/O voltage range (for all voltages) from MIL to Custom or Custom to MIL in the Project Settings UI and saving the changes no longer causes Libero to crash.
Data exported using the Record Action function is incorrect. | Record Actions now reports the proper values.
Load probe feature always opens to the default location. | SmartDebug now opens the last opened directory instead of the default location.
Charts do not show whether training fails in DDR Debug mode. | SmartDebug now displays training charts even if training fails.
A training iteration counter has been added to the SmartDebug GUI. | The SmartDebug GUI now displays an iteration counter and reports a warning when the reset counter value exceeds 10.
Incorrect result on write calibration in DDR Debug function. | SmartDebug includes additional checks to identify write-calibration failures.
`SD_WRITER`: Missing connection for bus slice. | Libero now detects missing slice nets and write assignments on component generation.
PF_IO: Complete matrix of registered versus non-registered BIDIR I/O. | Libero configurator now allows Input IOFF, Output IOFF, or Enable IOFF for bidirectional I/Os to be selected individually.
`PF_IOD_OCTAL_DDR` configuration issues. | Libero IO configurator now allows single-ended DQS to be selected for AP SRAM memory.
`PF_IOD` GUI does not allow non-integer frequencies. | The PF IOD configurator now accepts non-integer frequencies.

Rev: 2025.2

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