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# 1.5 Migrating Designs to Libero SoC

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## 1.5.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2025.2. For more information about updating a core version, see the section Updating a Core Version.

Table 1-1.Core Enhancements and Upgrades
Core | 2025.2 Version | Status | Comments
--- | --- | --- | ---
PF_CCC | 2.2.222 | Production | Added fix for incorrect configurator-generated settings for PolarFire DLL in Phase Generation Mode.
PF_IO | 2.0.106 | Production | Added support for Delay mode feature with two options, Narrow and Wide, with delay tap range support of 0-127 and 0-255, respectively.
PF_IOD_GENERIC_RX | 2.1.116 | Production | Added support for fractional clock parallel data in fractional dynamic mode.
PF_IOD_OCTAL_DDR | 2.0.113 | Production | Improved configurability, timing, and simulation accuracy for IOD Octal DDR. See the IOD Octal DDR Enhancements section.
PF_RGMII_TO_GMII | 1.3.111 | Production | Repackaged to include the latest PF_IOD_GENERIC_RX version.
PF_SRAM_AHBL_AXI | 1.2.115 1.2.116 | Production | High-reliability options added for PF_SRAM_AHBL_AXI with CoreAHBLSRAM_PF v3.0 and CoreAXI4SRAM v3.0. See the Enhanced PF_SRAM_AHBL_AXI with High-Reliability Options section.
PF_SYSTEM_SERVICES | 3.0.104 | Production | High-reliability options added for PF_SYSTEM_SERVICES with CoreSysServices_PF v4.0. See the Enabled Fault Tolerance for PF_SYSTEM_SERVICES section.
PF_SPACEWIRE_RX_PHY | 1.0.110 | Production | Added the option to expose the Failsafe ODT_EN port for the SPACEWIRE_RX core interface. See the Added Failsafe ODT_EN Support for SPACEWIRE_RX section.
RTG4_SRAM_AHBL_AXI | 1.0.123 1.0.124 | Production | High-reliability options added for RTG4_SRAM_AHBL_AXI with CoreAHBLSRAM_PF v3.0 and CoreAXI4SRAM v3.0. See the Enhanced RTG4_SRAM_AHBL_AXI with High-Reliability Options section.

## 1.5.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right-click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

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