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# 9.4 Software Features and Enhancements

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## 9.4.1 SmartDesign Enhancements

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### Status Icon

A status icon now appears on instances in a SmartDesign canvas highlighting various states of an instance representing scenarios such as:

- A newer core version is available for use in the vault or repository.
- The port-list of the component or module has changed.
- The component or module has been deleted.

The status icon, along with the color of the instance and the tooltip message on the instance, helps to inform users about the state of the instance and take further actions as needed.

### Enhanced Smart Search and Connect Widget

Typing Ctrl+F (the usual keyboard shortcut for Find) in a SmartDesign now opens the new enhanced Smart Search and Connect widget, which can be used to search, filter and connect objects in the canvas in an effective and intuitive way.

### Member Pins of Bus-interfaces (BIF)

Member pins of bus-interfaces (BIF) promoted to the top are now prefixed by the BIF name. When promoting bus interface pins to the top, the underlying ports will get the bus interface name as a prefix. When a top-level bus interface port is renamed, all the underlying ports will also be renamed to match the parent name.

### Generating System Builder Type Core Components

Generating System Builder type core components such as the PolarFire DDR cores is now approximately 1.75x faster compared to the previous release. Opening the View Memory Map widget also is much faster now for a SmartDesign, which has one or more System Builder type core components such as the PolarFire DDR cores instantiated under its hierarchy. Generating such SmartDesign components also is much faster compared to the previous release.

### Configure Design Initialization Data and Memories Tool Window

The Configure Design Initialization Data and Memories Tool window now opens almost instantaneously for bigger designs compared to the time it would take to open in the previous release.

## 9.4.2 Timing Report Explorer – New Graphical Statistics Report

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The Timing Report Explorer tool includes an Insights button with a slack distribution feature. This feature displays a slack distribution histogram of the slacks subset considered by the tool.

## 9.4.3 SmartTime – User SET

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SmartTime in Libero SoC v2022.1 has been enhanced to allow users to export and import user defined path sets and reuse them in different projects.

## 9.4.4 SmartPower Enhancements

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### VCD Import Improvements

Import VCD offers now the ability to annotate specific blocks in the design hierarchy.

### Runtime for Vectorless Activity Annotation

Runtime for the vectorless activity annotation in SmartPower has been reduced significantly by using parallel execution.

## 9.4.5 SmartDebug Option to Export Contents of eNVM and sNVM

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SmartDebug now supports a file export feature for exporting clients and pages data to an output text file. This feature is available using the export buttons on the sNVM Debug and eNVM Debug windows in the Libero SoC v2022.1. Alternatively, you can use the `export_envm_data` and `export_snvm_data` Tcl commands to export eNVM and sNVM clients or page data.

### Export sNVM Client Data

    export_snvm_data -client {INIT_STAGE_1_SNVM_CLIENT} -startpage 202 -endpage 219 -file_name {C:/Users/libero/snvmclientdata.txt} -uskKey {0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0:0}

### Export sNVM Page Data

    export_snvm_data -startpage 1 -endpage 1 -file_name {C:/Users/libero/snvmpagedata.txt} -uskKey {0}

### Export eNVM Client Data

    export_envm_data -client {BOOT_MODE_1_ENVM_CLIENT} -startpage 0 -endpage 127 -file_name {C:/Users/libero/envmclientdataafterread.txt}

### Export eNVM Page Data

    export_envm_data -startpage 1 -endpage 1 -file_name {C:/Users/libero/envmpagedata.txt}

## 9.4.6 Comprehensive FlashPro Express Troubleshooting Table

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Improved and updated the exit codes troubleshooting tables for the SmartFusion2/IGLOO2, PolarFire, RT PolarFire, and PolarFire SoC families to be in sync with FlashPro Express software. For more information, see the FlashPro Express User Guide .

## 9.4.7 Synplify Pro and Identify

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The Synplify Pro and Identify tools bundled in Libero SoC v2022.1 have been upgraded to SynplifyPro S-2021.09M and Identify Debugger S-2021.09M versions. Key enhancements are:

- Write Byte enable inference for Dual-port LSRAM support for PolarFire, RT PolarFire, and PolarFire SoC family devices.
- Pre-layout delay on Global nets sourced from I/O or fabric.
- Removal/recovery timing analysis of Async paths.
- Support for the `syn_reduce_controlset_size` attribute.
- Support for Microsoft Windows 10 - 11th generation Intel i7 and i9 processor.
- Synplify Pro and Identify are now fully supported on Ubuntu 20.04.3 LTS in addition to Ubuntu 18.04.

The new attribute `syn_reduce_controlset_size` specifies the minimum size of the unique control-set on which control-set optimizations can occur. Control sets are unique combinations of clock, clock-enable, and sync-reset signals. For PolarFire, RT PolarFire, and PolarFire SoC, the threshold for sync-reset inference is 6.

### Usage Syntax

FDC

      define_attribute {v:object} syn_reduce_controlset_size value
      define_global_attribute syn_reduce_controlset_size value

Verilog

      object /* synthesis syn_reduce_controlset_size = value */

VHDL

      attribute syn_reduce_controlset_size : integer;
      attribute syn_reduce_controlset_size of object : objectType is value;

## 9.4.8 Red Hat Enterprise Linux 7.9 and Ubuntu 20.04.3 LTS Support

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Starting with v2022.1, Libero SoC is supported on the Red Hat Enterprise Linux®/CentOS™ 7.9 and the Ubuntu® 20.04.3 LTS operating systems.

Rev: 2025.2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.