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# 7.5 New Silicon Features and Enhancements

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## 7.5.1 PolarFire, RT PolarFire, and PolarFire SoC

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### 7.5.1.1 Updated Design Initialization and Data Report

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The Design Initialization Report has been updated with a new table called Used Modules. This table lists the Corner and ICB macros used in a design. Some additional macros, such as Tamper, UJTAG, SPI, Sys Services, and INIT, are now reported as used if present in the user’s design.

### 7.5.1.2 New INTx Interrupt Selection

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In the PCIe core configuration GUI, when the INTx interrupt type is selected, the Interrupt Mask register is updated during automatic power-up/DEVRST_N initialization to reflect the correct setting.

### 7.5.1.3 New Clock Frequency Monitor Setting

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A new option has been added to enable or disable clock frequency monitor in the `PF_TAMPER` and `PFSOC_TAMPER` cores.

### 7.5.1.4 ECC Pipeline Registers in PF_TPSRAM are TMRed

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TMR functionality is enabled for the soft logic used in the ECC pipeline registers of`PF_TPSRAM`.

### 7.5.1.5 TMR of Registers in External Feedback and Post-divider Modes

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TMR functionality is enabled for the soft logic used in Post-Divider and External Feedback modes.

### 7.5.1.6 New TVS Monitor for SmartDebug

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A new SmartDebug feature has been added to monitor both internal voltage supplies and die temperature from the TVS outputs, and log the values across specified time intervals.

### 7.5.1.7 SmartDebug FPGA Hardware Breakpoint Enhancements

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The following FPGA hardware breakpoint enhancements are supported:

- Any `CLKINT` selection through the `auto_instantiate_fhb` NDC command

- Automatic timing constraints
- New report
- Support of encrypted components

## 7.5.2 PolarFire SoC

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### 7.5.2.1 New MSS Interrupt Map Report

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Users can export an interrupt map report for an MSS component. This report file represents the entire connection hierarchy of MSS interrupt pins. For PolarFire MSS components, all the hierarchy pins are combined within a `MSS_INT_F2M[63:0]` bus.

### 7.5.2.2 New PFSOC_TAMPER Core Including eNVM POR Digest Check

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In the PolarFire and PolarFire SoC Tamper macro, POR digest check can be enabled for sNVM, Fabric, and Security. As a result the `PORDIGEST` bit settings for all Digest check options in both PolarFire and PolarFire SoC have been changed. eNVM is present in PolarFire SoC only and not in PolarFire. For this reason, a separate TAMPER core was created for PolarFire SoC. In the PolarFire SoC TAMPER core, a new option has been added to support POR Digest check for eNVM.

### 7.5.2.3 New OWP Protocol in Bitstream Temporarily Undoes Locks

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The One-way Passcode (OWP) protocol is used for overriding locks via a bitstream without requiring any interaction with an external intelligence (for example, IAP/Auto-Update flow). The primary use-model is to support one-time bitstream updates, where the one-way pass code is bound to a given bitstream. The bitstream created with OWP temporarily undoes locks that would otherwise prevent the bitstream from being used. When the bitstream is complete or terminates for any other reason, locks are restored to their original non-volatile states. The bitstream created with OWP is protected by the standard bitstream encryption and authentication mechanisms.

### 7.5.2.4 IBIS for SGMII, DDRIO, and MSSIO

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Special I/O attributes `MSSIO`, `DDRIO`, and `SGMIIIO` are now supported for PolarFire SoC. These I/O attributes help you to arrive at the correct power data and IBIS data.

## 7.5.3 RTG4, SmartFusion2, and IGLOO2

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### 7.5.3.1 New Option for Time between RESET Release and CKE Assertion

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The new GUI option Time b/w RESET release and CKE assertion has been added to RTG4 FDDR, SmartFusion2 MSS-DDR, FDDR and IGLOO2 HPMS DDR ,and FDDR Configurator. This option helps you specify any custom time (non-default) value between the `RESET` signal release and assertion of the `CKE` signal.

For more information, see the following device-specific DDR memory controller configuration user guides:

- PolarFire Family Memory Controller User Guide
- UG0573 RTG4 FPGA DDR Memory Controller User Guide
- RTG4 DDR Memory Controller Configuration User Guide
- RTG4 DDR Memory Controller with Initialization Configuration User Guide

### 7.5.3.2 Back-annotated Simulation of Differential I/O Connected to the FDDR Controller Hard-IP Block

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The RTG4 DDR3 simulation model has been updated to address gate-level simulation failures.

## 7.5.4 Programming

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### 7.5.4.1 FlashPro 6 Improvements - Mailbox Bug Fix, Programmer Access Lag

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The Mailbox feature is used to transmit large amounts of data to and from the host. The mailbox transmits up to 4K-Bytes of data at a time. Because of this, a handshake mechanism is implemented to make sure the PC and firmware applications are in sync. FlashPro Express uses mailbox for SPI-Flash read operations only.

The following issues have been fixed for the mailbox feature:

- Timeout during SPI-Flash read operations
- Data corruption between pages

Rev: 2025.2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.