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# 3.2 Changes That Address Important Issues

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## 3.2.1 RTG4

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### 3.2.1.1 PLL Calibration Updates for RTG4FCCCECALIB v2.2.100, FDDR v2.0.200, and SerDes v2.0.200 Cores

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- Updated the rules for selecting the high-VCO frequency used to implement the enhanced PLL calibration introduced along with CN19009 and its addendums.
  - Prior to v2.2.100, the allowed ratio of high-VCO frequency to actual-VCO frequency used during PLL calibration was between 1.5x to 1.9x of the user configured actual-VCO frequency.
  - Starting with v2.2.100, the allowed High-VCO frequency selected by the RTG4FCCCECALIB core is limited to the reduced range of 1.25x to 1.5x of the actual-VCO frequency. The change was applied to mitigate a rarely encountered loss of lock at cold operating temperatures for specific core configurations using VCO speed-up ratios on the higher side of the previously allowed range.
- Reduced the enhanced PLL calibration high-VCO dwell time from 150 us to 100 us in the RTG4 SerDes PCIe/XAUI SPLL calibration sequence used with a CoreABC initialization subsystem, to ensure continued successful PCIe endpoint enumeration on newer generation host CPUs. The same update was applied to the RTG4FCCCECLAIB and FDDR cores to ensure consistency for all cores using PLL calibration.
- Recommended actions related to the PLL Calibration updates:
  - No action is required for:
    - Designs that have successfully completed full functional and system testing on each production unit over the full operating conditions.
    - Designs not using the PLL in RTG4FCCECALIB, the FDDR FPLL, or the SerDes SPLL (PCIe/XAUI).
  - For ongoing designs using fabric PLLs in systems where the operating temperature can fall below 0°C, perform the following steps and re-run the design flow:
    - Upgrade the design to Libero SoC v2025.1, and observe a warning message in the log window.
    - Update instances of RTG4FCCCECALIB to v2.2.100 and regenerate the core.
    - Update instances of RTG4FDDRC or RTG4FDDRC_INIT to v2.0.200 and regenerate the core.
      - For RTG4FDDRC, manually copy the updated FDDR_init.txt initialization program into the user CoreABC initialization subsystem.
    - Update instances of RTG4 SerDes cores using the SPLL (for PCIe or XAUI interfaces) to v2.0.200.
      - Includes RTG4 cores: PCIE_SERDES_IF, PCIE_SERDES_IF_INIT, NPSS_SERDES_IF, NPSS_SERDES_IF_INIT
      - For SERDES cores without auto initialization, including PCIe, copy updated SERDES_*_init_abc.txt program into CoreABC.
      Note: The Libero SoC v2025.1 design flow will error out during netlist Compile if older core versions are detected.
  - For new designs, use Libero SoC v2025.1 and the latest RTG4FCCCECALIB v2.2.100, FDDR v2.0.200, and SerDes v2.0.200 cores.

### 3.2.1.2 FDDR 16-bit and 8-bit Width Modes with ECC Enabled

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- Updated IP core top-level DQ_ECC port bit mapping to device package pin FDDR_DQ_ECC[#] for proper ECC functionality.
- RTG4 DDR DQ works as expected when SECDED is enabled.
- When opening a pre-2025.1 RTG4 design that uses the RTG4 FDDR in x16 or x8 modes, the design is invalidated to a pre-synthesis state.
- Applicable for designs that contain instances of the RTG4FDDRC or RT4FDDRC_INIT core configured for 16-bit or 8-bit DQ width with ECC enabled.
- The core component must be updated to an RTG4 version 2.0.200 or later and regenerated to continue with the design flow.
- Review the latest RTG4 Package Pin Assignment Table (PPAT) available on the Microchip website to ensure the board layout has connected the correct FDDR_<E|W>_DQ_ECC<#> package pin to the DDR memory device holding ECC data, depending on the DQ bit-width in use.

## 3.2.2 PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC

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### 3.2.2.1 DDR3, DDR4, LPDDR3 Fabric Core Updates

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- Support for ZQCS command
- Re-initialization enabled to restart DDR training
- Fast simulation training IP
- Removal of ODT activation setting on read
- Support for CK/CA additive offset “0” value in the configurator for the DDR3/DDR4/LPDDR3 controller. Additionally, the Read ODT option has been removed from the configurator

### 3.2.2.2 PF_XCVR CDR 3G, HD SDI

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- Updated transceiver register presets for “Lock to Data with 2X Gain” receiver mode to account for a wider variety of board noise environments.
- The XCVR CDR PLL mode in the transceiver lane now locks successfully when the Lock Mode is set to Lock to Data with 2x Gain, even under pathological data patterns.

### 3.2.2.3 IOD LANECTRL Isolation from Unrelated Active DLL

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Enhanced DRC to ensure that IOD LANECTRL instances are isolated from unrelated active DLL instances when a design has multiple IOD interfaces such as MIPI, Generic TX, and Generic RX interfaces.

### 3.2.2.4 IOD RX_CLK_ODT_EN for LVDS Failsafe

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- Connected RX_CLK_P to HS_IO_CLK when “Clock to Data Relationship” is dynamic, centered, or aligned.
- New ODT_EN LVDS Failsafe functionality for 'IOD_RX' core allows users to avoid time-zero failures when the clock-to-data relationship is not fractional.

### 3.2.2.5 CoreFIR_PF: Constant Coefficient of Inferred MACC_PA_BC_ROM

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Synplify Pro versions V-2023.09M (Libero SoC v2024.1) and V-2023.09M-3 (Libero SoC v2024.2) could write a hexadecimal prefix for a binary format constant coefficient of an inferred MACC_PA_BC_ROM instance in the generated VM netlist. This primarily affected user-defined coefficients of CoreFIR_PF components. Synplify Pro version V-2023.09M-5 in Libero SoC v2025.1 now generates proper format of the inferred constant coefficients.

## 3.2.3 PolarFire SoC Standalone MSS Configurator

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### 3.2.3.1 MSS_DDR 16-bit Width with ECC Enabled

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Updated MSS Configurator component XML to enable correct ECC byte-lane and ensure successful DDR memory training.
Note: MPFS HAL versions later than v2.3.105 is required from the PolarFire SoC GitHub to use this change.

## 3.2.4 RT PolarFire SoC

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### 3.2.4.1 CG1509 Package Update

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Updated package pin functions for RTPFS460ZT/ZTS/ZTL/ZTLS CG1509.

Rev: 2026.1

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