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# 2.6 Migrating Designs to Libero SoC

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## 2.6.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2025.1. For more information about updating a core version, see section Updating a Core Version.

Table 2-1.Core Enhancements and Upgrades
Core | 2025.1 Version | Status | Comments
--- | --- | --- | ---
CORESMARTBERT | 2.11.100 | Production | Core update to use the latest XCVR core version.
PF_DDR3 | 2.4.131 | Production | Core update for ZQCS command, Reinitialization, ODT Removal, CK/CA additive offset value correction and cleaning up simulation warnings. See section PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC.
PF_DDR4 | 2.5.120 | Production | Core update for ZQCS command, Reinitialization, ODT Removal, CK/CA additive offset value correction and cleaning up simulation warnings. See section PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC.
PF_INIT_MONITOR | 2.0.308 | Production | New FC1509 package added for RTPF500ZT/ZTS/ZTL/ZTLS RT PolarFire devices and for RTPFS460ZT/ZTS/ZTL/ZTLS RT PolarFire SoC devices.
PF_IO | 2.0.105 | Production | Core update for the clock edge selection for the RX/TX/OE register.
PF_IOD_TX_CCC | 1.0.131 | Production | Core update to produce TX_CLK_G output in 3.5 clock ratio.
PF_LPDDR3 | 2.3.125 | Production | Core update for ZQCS command, Reinitialization, ODT Removal, CK/CA additive offset value correction and cleaning up simulation warnings. See section PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC.
PF_XCVR_ERM | 3.1.206 | Production | Core updates for XCVR SDI presets - SD, HD and 3G.
PFSOC_INIT_MONITOR | 1.0.309 | Production | VDDI and calibration status enabled in PFSOC_INIT_MONITOR IP.
RTG4FCCCECALIB | 2.2.100 | Production | Allowed High-VCO frequency selected by the RTG4FCCCECALIB core is limited to the reduced range of 1.25x to 1.5x of the actual-VCO frequency. See section RTG4.
RTG4FDDRC |  | Production | Fix for DDR x16/x8 w/ ECC issue, FDDR FPLL calibration sequence update. See section RTG4.
RTG4FDDRC_INIT | 2.0.200 | Production | Fix for DDR x16/x8 w/ ECC issue, FDDR FPLL calibration sequence update. See section RTG4.
RTG4 PCIE_SERDES_IF | 2.0.200 | Production | Updated the enhanced PLL calibration to reduce the High-VCO frequency limit and to reduce the high-VCO dwell time from 150 us to 100 us in the RTG4 SerDes PCIe/XAUI SPLL calibration sequence. See section RTG4.
RTG4 PCIE_SERDES_IF_INIT | 2.0.200 | Production | Same as above.
RTG4 NPSS_SERDES_IF | 2.0.200 | Production | Same as above.
RTG4 NPSS_SERDES_IF_INIT | 2.0.200 | Production | Same as above.

## 2.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right-click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

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