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# 10.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2021.3 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 10-4.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Summary | Resolution
--- | --- | ---
00967427 | For SmartFusion2 and IGLOO2 Libero designs, if the customer selected an eNVM component only in bitstream along with the sanitize all eNVM pages option, the output of Generate Bitstream, Export Bitstream, and Export FlashPro Express Job produces incorrect bitstream file where running ERASE action will program eNVM instead of sanitizing eNVM. | This issue is fixed in Libero v2022.2.
763015 | Enhancement request for PCIe Class code issue. | Fixed the configured value reported for the `PCIE_PCI_IDS_DW1` register in the Design Initialization report.
493642-2841182125 | Simulation option for early and late flags. | Added the new option Enable delay line simulation to simulate early and late flags.
493642-2820557122, 493642-2819764435 | RTG4 FDDRC IP configuration parameters. | Fixed an issue related to the `TCCD` value of DDR3 for FDDR/MDDR cores.
493642-2782119315 | PolarFire IOD tap delays do not change with timing constraints. | See section External Timing Closure of IOD Interfaces.
493642-2677062271, 493642-2655936732 | Timing fails in ECF flow but passe in CCF flow. | To derive constraints accurately, Microchip recommends you use the IP configurators to generate your design's components when applicable (for example, CCC).
493642-2817875151,493642-2821376208 | Embedded FlashPro 6 programming failure on PolarFire SoC Icicle kit. | Fixed an issue where a programmer serial number starts with zero.
493642-2883414934, 00810431 | Failed to open the eFP6 HID Handle during programming. | Fixed an issue where a programmer serial number starts with zero.
493642-2759795158 | SmartFusion2 and IGLOO2 PCIe BFM `writemult64` is not working properly in simulation. | Updated the PCIe BFM simulation model to add a minor delay between execution of consecutive write commands.
493642-2866102670 | PolarFire IOD Debug - Eye Width. | Updated the GUI by changing Eye Width to Total Tap Delays
765748 | There is an issue with the `Top_hw_platform.h` file generated by Libero SoC v2021.1. | Fixed an issue with hierarchical names that prevented the `_hw_platform.h` file from generating properly.
769988 | Libero freezes on CCC IP generation for specific settings. | Fixed an issue where the PLL solver failed to find a solution and would hang.
791627 | RTG4 SmartDebug PRBS test. | Fixed the code to show Near-End Loopback as an option for all lanes.
798085 | BSDL file generation from Libero v12.6 and v2021.2 provides extra square brackets. | Removed extra brackets that were present around used pins when exporting a BSDL file.
806571 | CDC Synchronizer detection in Libero v2021.2. | In this release, SynplifyPro detects the synchronizer paths. The CDC report displays these paths as Safe CDC.
814348 | Missing path (reg-reg) if `clk` is bidirectional. | Fixed clock constraints set on bi-directional I/O so they are no longer ignored.
816645 | Actual frequency is not reported properly in the configurator. | Fixed an issue where the solution found by the PLL solver was not displayed properly in the configurator.
820605 | Ignored constraints in Constraint Coverage Report. | Fixed an issue where clock constraints set on bi-directional IO were ignored.
829923 | `PF_INIT_MONITOR` configuration window issue for `MPF300TS-FC784M`. | Fixed an issue where information about IO banks was missing for certain die/packages.
007765573, 00775744, 00764636 | Octal Phy Differential DQS output. | See section PolarFire, PolarFire SoC, RT PolarFire – Octal PHY Differential DQS Output.
00782198, 00797168 | FlashPro Express/Libero crashes in Windows 10. | Fixed an issue related to parallel port type programmer enumeration.
493642-2609577092 | Warning in Constraints Editor for `set_max_delay`. | Fixed an issue where timing constraint checker failed to detect paths ending on a bi-directional I/O.
493642-2759080279 | For SmartFusion2 and IGLOO2 EPCS, Libero was not able to create an `ENVM_INIT.mem` file. | In the Libero SoC Design Flow User Guide added a note about setting one testbench as Active Stimulus when there are multiple testbenches in Stimulus Hierarchy HDL Testbench and Create a New SmartDesign Testbench.
493642-2798260961 | For RTG4, negative power was reported in the CLK domain. | Fixed an issue related to incorrect I/O data.
493642-2824979978 | Issue in customer design with Tcl command report constraints_coverage | Fixed an issue where the constraint coverage report was incorrectly counting output clocks as unchecked.
493642-2848099507 | The SmartFusion2 and IGLOO2 warning message `A_DOUT_CLK is not synchronized to A_CLK in pipeline mode` has been observed when the clock gating is used. | Fixed an issue in the SmartFusion2 and IGLOO2 SRAM simulation model so that a warning no longer appears when a clock resumes after a pause.
00759452 | The simulation is not working for SERDES PMA lanes through DRI in Libero v2021.1. | Fixed an issue in the PolarFire DRI simulation model to support simulation for quad 3, 4,, and 5 of the `SerDes` lane.
493642-2850665818 | MT688 and MT659 warnings in SynplifyPro. | Added information about MT688 and MT659 warnings messages to the SynplifyPro OEM Message Reference PDF file for this release.
493642-2851373204 | Update UG0590 RTG4 FPGA Clock Conditioning Circuit with suggestions for PLL not locking in simulation. | Added a note and screen shot to the miscellaneous section to the UG0590 RTG4 FPGA Clock Conditioning Circuit.
493642-2854884573 | The SmartFusion2 Tcl command `prbs_test ​-read_counter` returns an error. | Fixed an issue related to the algo file.
493642-2855980729 | RTG4 power calculator issue. | Fixed the drive strength mapping discrepancy for a couple I/O standards in the MSIO bank type.
493642-2860470396 | SmartTime: problem when selecting different paths to add constraints. | Fixed an issue related to a multicycle path context action in SmartTime that always selected the first path instead of selecting the selected path.
493642-2865348582 | CSV Timing reports generated by running Tcl scripts have content in text format. | Fixed the report format check to ignore letter-case checking.
493642-2870996997 | Inconsistent behavior in SmartTime for max delay constraint | Fixed an issue related to a path disabled by clock group constraints from being analyzed if a max-delay was set.
493642-2893267402 | Issue with naming of clock names with timing analysis in Libero v2021.1 and v2021.2. | Fixed a clock constraint merge when a clock is set with its name matching the clock source of another existing clock.
493642-2856208423 | Need 64-bit FlexNet binaries (`actlmgrd`, `lmgrd`, and `lmutil`) that run in a 64-bit RHEL/CentOS environment. | See section 64-bit Licensing Daemons.
493642-2832309098 | Improve programming error message. | In the FlashPro Express User Guide , added a PolarFire exit code with error code 4 (related to loss of USB packets while performing an action using FlashPro5 or embedded FlashPro5 ).
00804453 | Place and Route error with migration option for PolarFire device. | Fixed the error message to clarify the issue and explain how to resolve the error. Users experiencing this error must regenerate the Initialization Monitor core, and then rerun the tool flow.
00821909 | Incorrect Signal Integrity Configuration box. | Updated the Signal Integrity dialog box screen shot.

Table 10-5.Customer-Reported Defects and Enhancement Requests (No Case Numbers)
Summary | Resolution
--- | ---
MEMORY_MAP: v12.3 SmartDesign Connect DRC |
Libero v12.5SP1 Segmentation Fault error during Place and Route. | Fixed a crash that occurred when all registers were used in timing constraints.
Runtime issue in constraint editor with from/to filters. | Improved runtime when searching for from/to objects in timing constraint editor.
Reporting device integrity value. | Fixed factory integrity and device integrity values to reported with a pass or fail status.
The `FLASH_GOLDEN` pin BSDL safe value should be 1. | Fixed the safe value for the `FLASH_GOLDEN` pin in BSDL file to 1.
Change for SmartFusion2 and IGLOO2, the CCC GUI Lock delay description. | Updated the Lock Delay message from `"Lock Delay: Number of Reference clock cycles...` to `Lock Delay: Number of Post divided Reference clock cycles...`.
For SmartFusion2 and IGLOO2, an error-out would occur when programming all zeroes in page 0 for Rev A 090 and150 parts. | Updated the PROGRAM action to check and error-out when programming eNVM page 0 is filled with zeros for M2S090 and M2S150 Rev A devices.
Signal integrity modifications in the graphical user interface persist across tool launches. | Added tool tips and text to the signal integrity parameters in the Signal Integrity view to make the view for intuitive.
Check connection between different ID widths for AXI interface. | Added an ID/data width mismatch DRC. If a mismatch occurs between ID widths, warning messages appear in the log window.
Driver issues in FlashPro 5 force the application to stop working. | Fixed an issue related to older versions of FTDI drivers, with updates to the latest FTDI drivers.
Libero v2021.2 router failed in high-utilization project. | Fixed a check to make sure the flow stops if Libero cannot create the regional clock region when the region does not exist physically. The new error message indicates the IOD placement may not be legal and advises users to move the IOD to a different lane.
`BIBUFF_DIFF` sourced clock domain shows no re-to-reg timing | Fixed an issue where clock constraints set on bi-directional I/O were ignored.
Issue with RAM Initialization when the port width is not aligned on a byte boundary. | Added an info icon at RAM Initialization to indicate when the Write Port width is not aligned on a byte boundary.
`PF_TAMPER: ZMODE` default set to 3, non recoverable | Changed the default setting for Zeroization mode from Non recoverable to Like New.
Revert SmartTime changes for Commit, as it is affecting the user sets flow. | Enabled the Commit button.
RTG4 Macro Library User Guide | Updated the Macro Library User Guide for RTG4 as follows: Added an additional references table that contains references to DDR and SERDES hardcore blocks. Added an appendix on how to access the IP core documentation from within the Libero SoC Design Suite.
Configuring RTG4 `CCC_#_GL_#` in Bypass mode to source the `CLK_50MHz` ECALIB clock causes a deadlock issue. | Fixed an issue related to the `CCC_*_GL*_Y*_EN` connecting to VCC when the corresponding `CCC_*_GL_*` was configured in Bypass mode.
Issues when copying HDL+ core instances. | Fixed an issue that prevented parameters from working as expected when copying and pasting the HDL+ core instance.
Export Bitstream for SmartFusion2 and IGLOO2 failed for SVF. | Fixed an issue related to referencing an undefined function when exporting SVF for SmartFusion2 and IGLOO2 devices.
Erase action present when it is not applicable for eNVM flow. | Removed the Erase action from the list of programming actions in FlashPro Express/Libero when there is an eNVM-only design with sanitization off.
Incorrect Verify Failure from STPL in the FLASHPRO log. | Fixed the VERIFY action error message to print the correct component type (sNVM vs Security).

Rev: 2025.2

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