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# 12.4 Software Features and Enhancements

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## 12.4.1 Smart High-Level Synthesis (SmartHLS) general release v2021.2

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Libero SoC v2021.2 includes the first general release of Smart High-Level Synthesis (SmartHLS) tool.

SmartHLS is an Eclipse-based integrated development environment that accepts C++ software code as input and generates a SmartDesign IP component (Verilog HDL) as output. Hardware engineers can instantiate the generated SmartDesign IP component in the SmartDesign canvas available in Libero SoC design suite to build an FPGA system.

The SmartHLS software requires a free license that you can request in the Microsemi SoC Portal. Use the following procedure to request the free license.

1. Log into the Microsemi Customer Portal (http://soc.microsemi.com/portal) and click the License and Registration link.
2. Click Request Free License.
3. Click SmartHLS one-year Disk ID License for Windows or SmartHLS one-year Floating License for Windows or Linux Server.
4. On the next page, enter the hard Disk ID or MAC ID of the machine based on the selected license option, and then click the Submit button.
   A new `license.dat` file will be emailed to you, enabling you to use SmartHLS.
5. When you receive the `SmartHLS license.dat` file, open it, copy the content, and add it to your existing Libero software license file with the similar Libero license option (Disk ID or MAC ID). For example, if you generated a node locked license for the SmartHLS tool, add the SmartHLS license file content to the Libero node locked license.
   For more details, see the:
   - Online SmartHLS v2021.2 release notes. The release notes can also be found in the Libero installation under `SmartHLS-2021.2/docs/releasenotes.html`.
   - Microchip SmartHLS User Guide.

## 12.4.2 SmartDesign Enhancements

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Libero SoC v2021.2 adds new features to the SmartDesign tool enhancing the front-end design entry capability.

- Hierarchical SmartDesign Creation from within the Canvas
- Full Copy/Cut/Paste Support within a SmartDesign and across SmartDesigns
- New Smart Search and Connect feature replaces Quick Connect
- Synthesis Attributes support

Note: Copy and paste functions for HDL+ core instances are not yet supported and should not be used in the release. This will be fixed in Libero SoC v2021.3

For more details, see the SmartDesign User Guide .

## 12.4.3 Bitstream Digest

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Prior to Libero SoC v2021.2, the calculated digest of each bitstream component (Fabric, Security, eNVM, etc.) that gets logged during bitstream export did not include metadata such as the software version, design version, design name, and advanced bitstream options for PolarFire SoC. Libero SoC v2021.2 calculates the digest over the entire bitstream, including the metadata. This is embedded inside the bitstream in plaintext, logged during bitstream generation and export tools in Libero SoC, and shown in the FlashPro Express UI by hovering over the info icon of the device. This feature is available for SmartFusion2, IGLOO2, PolarFire, RT PolarFire, and PolarFire SoC families.

For more details, see the Libero SoC Design Flow User Guide for the specific device family.

## 12.4.4 Out-of-Context Derive Constraints Utility for Custom Flows

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Libero SoC v2021.2 adds a stand-alone tool to derive constraints for running synthesis outside the Libero project (custom design flow). The tool needs a Tcl script that specifies the HDL source and SDC timing constraints from the various configurators to generate SDC files for both synthesis and back-end tools.

For more details, see the Custom Flow User Guide .

## 12.4.5 Timing Constraint Enhancements: Multi-cycle Start and End Options

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Libero SoC v2021.2 adds support for `-start` and `-end` options to the `set_multicycle` SDC timing constraint. These options allow users to specify which clock period is applied for the additional cycles.

- For `-end`, the capturing clock period is applied, which is the default for setup analysis.
- For `-start`, the launching clock is applied, which is the default for hold analysis.

Existing designs without `-start` or `-end` will not be affected, as the defaults are unchanged.

For more details, see the SmartTime Static Timing Analyzer User Guide .

## 12.4.6 Ability to Create and Select Synthesis and Identify Implementations

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Libero SoC v2021.2 adds the ability to create and select Synthesis and Identify implementations from Libero's synthesis configuration.

Running synthesis on a newly created Synthesis implementation will make it active. After creating a new Identify implementation, invoke SynplifyPro interactively, launch Identify Instrumentor on the selected implementation, instrument debug signals, and run synthesis to activate the Identify implementation in Libero.

Selecting a previous implementation will not restore the synthesis result or its configuration options. Update the synthesis configuration and rerun synthesis.

For more details, see the Libero SoC Design Flow User Guide .

## 12.4.7 SynplifyPro and Identify

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The SynplifyPro and Identify tools bundled in Libero SoC v2021.2 have been upgraded to version R-2021.03M. Besides enhancements and fixes, SynplifyPro is now fully supported on Ubuntu 18.04.

Generated names of signals and ports get renamed without special characters.

When the new attribute `syn_safe_cdc` is applied on a CDC path, it ensures that SynplifyPro will not add `syn_preserve`, `syn_replicate`, and `syn_allow_retiming` attributes, making these registers available for absorption during RAM and MATH block inference. SynplifyPro still reports the path as Safe and its description will be `syn_safe_cdc attribute applied`. The `syn_safe_cdc` can be applied on source, destination, or both. Example:

    reg ar /* synthesis syn_safe_cdc = 1 */;
    reg zr;
    reg sync;
    always @(posedge clk1)
    begin
        ar <= a;
    end
    always @(posedge clk2)
    begin
        zr <= ar;
        sync <= zr;
    end

For more details, see the Synopsys FPGA Synthesis SynplifyPro ME R-2021.03M User Guide.

## 12.4.8 Initiator/Target Nomenclature

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Libero SoC v2021.2 updates the nomenclature from Master/Slave to Initiator/Target in the SmartDesign Memory map view and reports, and PolarFire SoC standalone MSS configurator.

For more details, see the Libero SoC Design Flow User Guide .

## 12.4.9 Standalone Synthesis Flow

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Libero SoC v2021.2 users can synthesize designs outside the Libero SoC software using Synopsys SynplifyPro directly. When using this flow, the following additional steps are necessary to synthesize and implement a design:

- For Windows, make sure the <install location>/Designer/data/aPA5M/polarfire_syn_comps.v is added as a source file to the SynplifyPro project. This file contains module declarations with timing information for PolarFire primitives not known to Synopsys.
- For Linux, make sure the <install location>/Libero/data/aPA5M/polarfire_syn_comps.v is added as a source file to the SynplifyPro project. This file contains module declarations with timing information for PolarFire primitives not known to Synopsys.
- Many configured cores generate timing constraints. For optimal results, make sure these constraint files are passed to synthesis. These constraint files must also be imported into Libero along with the synthesis gate level netlist for optimal place, route, and timing analysis results. Core-generated constraint files must be modified so that constraints are expressed using the proper hierarchical name of the configured cores in the top-level design.

## 12.4.10 Discontinuation of ModelSim ME

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Starting with Libero v2021.2, only Modelsim ME Pro is officially bundled within Libero SoC. ModelSim ME integration has been discontinued in this Libero release. Users continue to have the flexibility of using previous and/or stand-alone versions of ModelSim ME.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.