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# 9.6 Migrating Designs to Libero SoC

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## 9.6.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2022.2. For more information about updating a core version, see section Updating a Core Version.

Table 9-9.Core Enhancements and Upgrades
Core | 2022.2 Version | Status | Comments
--- | --- | --- | ---
CORESMARTBERT | 2.9.102 | Production | For information, see section Enhanced SmartBERT Core for 10 Gbps Protocols.
PF_CCC | 2.2.214 | Production | For information, see section PLL Phase Alignment when Using Post-Divider or External Feedback Mode.
PF_CRYPTO | 1.0.110 | Production | Confirmed that in PolarFire SoC designs, DRC checks for PCIe and Crypto configurator when clock frequencies are between 70 and 125 MHz.
PF_DDR3 | 2.4.119 | Production | Integrated a new CCC core.
PF_DDR4 | 2.5.108 | Production | Integrated a new CCC core.
PF_INIT_MONITOR | 2.0.304 | Production | Improved the synchronizer circuit of the output latches.
PF_IOD_CDR_CCC | 2.1.108 | Production | Integrated new CCC core.
PF_IOD_TX_CCC | 1.0.125 | Production | Integrated new CCC core.
PF_IOD_GENERIC_RX | 2.1.109 | Production | Because the same port name cannot be added as input or output to symbol view, the `RX_CLK_G_IN` port now appears in symbol view if `RX_CLK_G` is used as an input port.
PF_IOD_OCTAL_DDR | 2.0.105 | Production | Integrated new CCC core.
PF_LPDDR3 | 2.3.117 | Production | Integrated new CCC core.
PF_QDR | 1.9.101 | Production | For PolarFire, a `COREQDR_PF` reset now propagates to IODs.
PF_RGMII_TO_GMII | 1.3.106 | Production | Integrated new CCC core.
PF_TAMPER | 1.0.209 | Production | For information, see section PF_TAMPER Enhancement to Latch Outputs when Using System Controller Suspend Mode.
PF_SPACEWIRE_RX_PHY | 1.0.107 | Production | For information, see section RT PolarFire SpaceWire RX PHY Core.
PFSOC_INIT_MONITOR | 1.0.304 | Production | Same improvements described in PF_INIT_MONITOR above.
RTG4FCCC | 2.0.204 | Production | For information, see section Changing Default Behavior of GLx_Yx_ARST_N Signals in the CCC Configurator.
RTG4FCCCECALIB | 2.2.007 | Production | For information, see sections Changing Default Behavior of GLx_Yx_ARST_N Signals in the CCC Configurator and Added Simulation Support for RTG4 PLL Feedback Delay.

## 9.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2026.1

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