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# 3.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2024.2 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 3-2.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Summary | Resolution
--- | --- | ---
493642-570495340, 493642-796226573, 493642-757930812, 01010822, 01248841, 01408429 | set_max_delay and set_min_delay needed added support for static timing analysis of the data path delay without clock path delay. | See section Ignore Clock Latency Constraint on CDC Data Paths.
01476217 | Libero SoC v2024.1 had an issue with IBIS model generation related to the /r character in the IBIS file on Windows operating systems. | This issue has been resolved.
01453580 | Zeroization results could not be read after a ZEROIZE_LIKE_NEW action was completed. | The DEVICE_INFO action has been updated to display the zeroization result/status when the device is in zeroized state.
01453358 | Place and Route fails on designs with heavily congested carry chain clusters. | Place and Route flow has been updated to handle long carry chain clusters for heavily congested designs.
01453038 | The Global Net report failed to list all the non-SET mitigated nets for RTG4 designs. | Each potential input of clock conditioning circuitry is now iterated to find all driving inputs.
01453014 | A warning message appeared for RTG4 SET and non-SET mitigated paths. | The clock conditioning circuitry configuration determines warning conditions.
01452899 | Libero crashed during Design Handoff for debugging for very large designs on Windows operating systems. | SmartDebug data can now be exported for very large designs without causing Libero to crash.
01452099 | Vref pin information did not appear in the Pin Report file. | The Pin Report file now contains Vref pin information.
01443887 | Installer was lacking RHEL 8.x support. | Support for RHEL 8.x has been added to the installer by modifying the supported OS script in the installer.
01439341 | An internal error in m_generic.exe occurred for PolarFire devices, but not for IGLOO2. | This issue has been resolved.
01436755 | Initialize Power Estimator window settings were not getting saved in Microchip Power Estimator. | Initialize Power Estimator now retains the saved settings.
01436743, 01472420 | M2S025T-FCSG158I could not be selected in the SmartFusion2 Power Estimator. | Support has been added for this die-package combination.
01435608 | A persistence issue occurred with the System Builder FDDR when used with DDR3 in 8-bit bus mode. | This issue has been resolved.
01430986 | An issue prevented the synthesis tool from evaluating expressions for designs with enum datatype declarations. | This issue has been resolved. Synthesis now passes satisfactorily for designs with enum datatype declarations.
01429854 | The Tcl commands set_as_target and unset_as_target were not working. | The filetype enum is now set according to the value provided by users in the command.
01428220 | The RECALCULATE ALL button in SmartTime was not active. | This button has been removed.
01423067 | Diff I/O in a bank with Low and Mid values always had a Mid value assigned. | If a combination of Low and Mid input common mode ranges (VCM_RANGE) is used for true differential inputs within the same GPIO bank, the input pairs that also enable the internal 100Ω On-Die Termination (ODT) resistor have a resistor accuracy tolerance percentage that follows the maximum percentage tolerance of the two ranges, per the device datasheet. Mixing VCM_RANGE settings in the same GPIO bank is currently allowed only during post-layout I/O editing.
01422069 | Improved SSN Analyzer DRC violation messages. | The DRC violation message in the Summary tab and the warning message in the Noise Report tab have been updated.
01420458 | For SmartFusion2 and IGLOO2, the VERIFY_DIGEST action did not print the freshly calculated digests. | The VERIFY_DIGEST action has been updated to print freshly calculated digests for Fabric/eNVM when these components are present in the bitstream.
01418457 | An issue occurred with the high-speed serial interface “signal integrity options” configurator. | The following INFO bubble has been added to have the configurator behavior inform users when they change the TX amp ratio to values other than 1200mV. `Adjustment to targeted dB values of the pre- and post- de-emphasis ratio settings are auto-generated based on 1200mV TX amplitude ratio. The "Signal Integrity GUI" does not automatically adjust the de-emphasis ratios to the correct dB for any other tx amplitude. User adjustment to other tx amplitude ratio values requires the user to manually adjust the settings through the "Edit Register" configuration window, after calculating the correct pre- and post- de-emphasis ratios using details in the RTG4 FPGA High-Speed Serial Interfaces User Guide.`
01415931 | A crash could occur when the timing engine analyzed paths without clocks. | This issue has been resolved.
01413236 | LVDS33 IOSTD setting support in Libero was missing for the XCVR REF_CLK. | Libero now supports LVDS33 IOSTD XCVR reference clock pins across PolarFire, PolarFire SoC, and RT PolarFire FPGA devices.
01410800 | A crash resulted from a multi-driver scenario from an intermediate netlist in the Automatic compile point flow. | This issue has been resolved and synthesis now passes satisfactorily.
01409449 | The External Setup value did not consider clock jitter during Maximum Delay Analysis. | The correct jitter value is now added to external delay check calculations.
01402440 | The IBIS model generated by the Libero SoC tool did not contain ODT information for the XCVR_REF_CLK. | xcvr_refclk IBIS models are now exported with default I/O settings.
01389577, 01385119 | When using Mi-V RV32 core, Verilog parameters were observed in the custom HDL+ configurator after modifying the core. | This issue has been resolved. Custom HDL+ core configurators now appear only in the Verilog parameters related to the current core.
01388294 | The reworked clock conditioning circuitry model could not identify that a source pin is a dedicated input pin when using get_ports and get_pins. | Jitter numbers for clock conditioning circuitry constraints now match if either get_ports or get_pins is used.
01373404 | LVPECLE33 was the default IOSTD for bi- and tri-I/Os when users selected LVVCMOS33 as a default I/O technology. | See section Project Setting Default I/O Technology LVCMOS 3.3V.
01371227 | The I/O Constraint Editor Package view crashed when placing a group of signals from Main Object Browser into the view. | This issue has been resolved and the crash no longer occurs.
01369314 | Depending on the user design, I/O glitches could be observed when exiting programming mode. Typically, this occurred at the end of program or verify operation. | The programming algorithms of SmartFusion2, IGLOO2, RTG4, PolarFire, and PolarFire SoC devices have been updated to avoid a potential I/O glitch when exiting programming mode.
01367141 | The MATH block model passed invalid multicycle constraints to timing analysis. | Libero constraint checker has been updated to issue an error message if it encounters any invalid multicycle path constraints.
01363398 | The PF_DDR3 and PF_DDR4 “CK/CA additive offset” value is not passed to the internal RTL logic. | See section “CK/CA additive offset” Parameter in the Training IP of DDR Controllers.
01360180 | Clock-to-clock uncertainty values were not considered during a Min-Delay repair. | This issue has been resolved to address design hold violations.
01358909 | The Power Estimator tool for PolarFire SoC devices did not include MSS I/Os. | MSS I/Os are now supported under the MSS&MDDR tab of the MPE.
01353583 | The reworked model for the RTG4 family did not report the correct path and jitter-estimation values. | In cascaded PLL scenarios, jitter values are now reported without errors.
01327940 | SmartDebug experienced crashes during project creation if the DDC file exceeded 1.5 GB in size. | Crashes are no longer experienced and DDC file sizes up to 2.8GB are supported.
01282955 | SmartDebug users could not control the Security Keys (UPK1 and DPK) in the DDC file. | Users can now control the exporting of Security Keys (UPK1 and DPK) resulting from DDC for the SmartFusion2, IGLOO2, PolarFire FPGA, RT PolarFire, and PolarFire SoC family.
01145463 | A SpaceFibre IP simulation failure could occur with PolarFire when using VCS simulator. | The PF_XCVR simulation model and library have been updated to align TX_DATA properly when LANEx_TX_WCLK is connected to a clock source other than LANE0_TX_CLK_G.
01137352, 01134979, 01319721 | The check for the Place and Route state reverted during the 0th iteration. | The multi-pass layout tool now bypasses Place and Route when it is in the NOT_RUN state and runs the Verify Timing.
01061565 | The reworked clock conditioning circuitry model or jitter estimation addresses the warnings seen with clock conditioning circuitry clocks. | No warnings are shown in Libero.log.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2024.2 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 3-3.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary | Resolution
--- | ---
IGLOO2 IBIS Export for custom temperature range. | Custom temperature ranges are supported in IBIS Export.
Streamline IGLOO2 Tamper Macro Zeroization options by removing the Recoverable option. | See section SmartFusion2 and IGLOO2.
Issues were observed with the Python script that injected ECC errors in simulation for RTG4 devices. | Resolved issues with the Python script to inject ECC errors in simulation for RTG4 devices. This includes small RAM depth, multiple RAM instances, and instance name inconsistencies.

Rev: 2025.2

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