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# 7.4 Software Features and Enhancements

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- Physical Memory Protection: Added Design Rule Checks for PMP and MPU expert mode fields in batch mode to prevent MSS generation for invalid values.
- MSS DDR timing: Updated MSS DDR configuration to account for the `tCCD_L` memory timing parameter.
- MSS Timing Shell export: Added support to export MSS Timing Shell information when HDL export is enabled.
- MSS DDR impedance display: Added display of the configured MSS DDR impedance value in ohms in the “MSS Impedance (Ohm)” column.

## 7.4.1 New set_external_delay SDC Timing Constraint to Specify External Feedback to PLL

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If a CCC External Feedback Delay goes outside the FPGA, you can add the `set_external_delay` SDC timing constraint to specify the delay of the external feedback path to the PLL. You can add, update, or delete `set_external_delay` constraints from the Editor in Constraint Manager. For more information about this constraint, see the topic SmartTime Tcl Commands in the Tcl Commands Reference Guide .

The timing report will include the feedback delay in the Clock generation step of the expanded path.

## 7.4.2 Export Interrupt Map Report for MiV Processors

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Users can export an interrupt map report for Soft Mi-V-based designs. This report file represents the entire connection hierarchy of the Mi-V processor interrupt pins. For more information, see the topic Exporting Interrupt Map Report in the Tcl Commands Reference Guide .

## 7.4.3 Timing Report Explorer Graphical Statistics

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The Timing Report Explorer in Libero SoC v2023.1 adds a path range option for Slack Distribution, Logic Level Distribution, Cell/Net Delay Pie, and Data charts. See the topic Slack Distribution in the Libero SoC Design Flow User Guide .

## 7.4.4 Programming and Debug Support for JTAG Chains Containing ProASIC3, IGLOO, SmartFusion, and non-Microchip Devices

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Libero SoC v2023.1 now supports JTAG programming and debug chains involving Microchip devices from ProASIC3, IGLOO, and SmartFusion families as well as non-Microchip devices. During chain programming, ProASIC 3, IGLOO,ProASIC3 nano, IGLOO nano, IGLOO Plus, and SmartFusion devices will be treated as bypass devices. In addition, VJTAG voltage levels across boards in a chain must be equal; otherwise, an error is generated. Integrated SmartDebug supports Post-Route Probe Insertion when devices are connected in a chain.

## 7.4.5 New Synplify Version

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The Synplify Pro and Identify tools bundled in Libero SoC v2023.1 have been upgraded to SynplifyPro T-2022.09M-SP2 and Identify Debugger T-2022.09M-SP2 versions. Key enhancements are:

- Enforce strict encryption rule of a single encryption envelope per module or entity-architecture. The single encryption envelope can be partial.
- RTG4 option (currently in beta) to initialize fabric registers using the initial value specified in RTL: `set_option -support_reg_init 1`

## 7.4.6 Ubuntu 22.04.1 LTS Support

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Starting with v2023.1, Libero SoC is supported on the Ubuntu 22.04.1 LTS operating system.

For a complete list of supported operating systems, see section Supported Operating Systems.

## 7.4.7 Help Documentation

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The PolarFire SoC Microprocessor Subsystem (MSS) Configurator documentation is also available as a part of the Libero SoC Design Suite Help Documentation webhelp. The webhelp features a very flexible layout and is designed to adapt to any screen size to provide an optimal viewing and interaction experience. Each topic and subtopic have an (Ask a Question) link that allows you to get answers to technical questions or to report inaccurate or incomplete information while viewing the help documentation. You can also use this link to file a technical support case with Microchip Technical Support.

- Click here to visit the new Libero SoC Design Suite Help Documentation WebHelp online.
- Click here to download a copy of the latest Libero SoC Design Suite Help documentation (in HTML file format) for offline reference. Extract the contents of the .zip archive and open index.html in a web browser of choice.

Important: You will need internet connectivity to view or download help documentation.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.