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# 1.5 Migrating Designs to Libero® SoC

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This section lists core enhancements and upgrades in Libero SoC v2026.1 and provides the procedure to update a core version.

## 1.5.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero® SoC v2026.1.

Core | 2026.1 Version | Status | Comments
--- | --- | --- | ---
PF_CRYPTO | 1.0.111 | Production | Updated tooltip and parameter-description guidance for AHB clock frequency requirements. See the PF_Crypto AHB Clock Frequency Guidance section for more details.
PF_IOD_GENERIC_RX | 2.1.117 | Production | Enhanced PF_IOD_GENERIC_RX configuration guidance for data rate versus fabric clock speed. See the PF_IOD_GENERIC_RX Data Rate and Fabric Clock Configuration Guidance section for more details.
PF_RGMII_TO_GMII | 1.3.112 | Production | Repackaged to include the latest PF_IOD_GENERIC_RX version.
PFSOC_TAMPER | 2.0.101 | Production | Disabled unsupported Fabric Digest Check option for RT PolarFire® SoC devices. See the PFSOC_TAMPER section for more information.

## 1.5.2 Updating a Core Version

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1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list is modified after updating, right-click the core component's instance in the SmartDesign and select Update Instance. Check for any pin/port disconnections and connect or tie them off as needed, then regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.