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# 1.6 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2025.2 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 1-2.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Summary | Resolution
--- | --- | ---
1590177 | Request to add DLL configuration registers in the Libero Initialization Report. | The Design Initialization Report has been updated to include DLL register configurations.
1322248 | Request to add argument to the `save_log` TCL command for error, warning and info messages. | Previously, the `save_log` TCL command dumped all log messages (info, warnings, and errors) into the output file. To allow message filtering, additional optional parameters (`-info`, `-warning`, `-error`) have been added, enabling users to select specific message types. This enhancement is backward compatible, as existing scripts continue to work without modification. This change doesn't break the older scripts as the newly added parameters are purely optional.
01593231 01637384 | Design Rule Check (DRC) relaxation was requested by customer on MSS I/O Bank2 for CAN interface with 2.5 V to avoid Single-Event Latchup (SEL) concerns with 3.3V MSS I/O voltages on RT PolarFire SoC devices. | DRC has been updated to support 2.5 V for CAN and I2C for all dies (including ES), packages and speed-grade. Additional LVCMOS I/O voltage support has also been added.
811815 | PF_IOD: The SDF timing arcs were not correctly generated to support BA simulation for static IODs. | Static timing check arcs for certain reset pins in IOD cell types have been removed from the SDF writer, resolving the issue.
1635458 | Issues were observed with the IBIS model generated using Libero SoC v2025.1 version specific to the LVDS ODT model. | IBIS is now exporting data correctly and so, issue has been closed.
860315 | Bottleneck analysis results were inconsistent in the Libero v2021.2 version. | Clock domain-based bottleneck reports can now be generated by selecting the clock from the "Set" category. An issue where this filtering did not work correctly has been resolved.
1578386 | PF_IOD_OCTAL_DDR core was missing default constraints. | All timing exception constraints can now be generated automatically. External timing constraints (such as `input_delay`, `output_delay`, `max_delay`, and `min_delay`) are not generated, as they depend on user board requirements.
1485133 | Anomalies were observed in the PMP set up for PolarFire SoC using MSS Configurator. | The PMP (Physical Memory Protection) view has been updated to address these issues, and correct behavior is now observed.
1475435 | An internal error (“Assertion Failed”) occurred after synthesis in a customer design. | The issue has been fixed by skipping the `X_INTERFACE_INFO` attribute when reading the VM netlist.
1614843 | Timing exception `set_disable_timing` was not working as expected for the IOD_TX blocks. | An issue with disabling CDC using the `set_disable_timing` constraint has been resolved. When multiple `set_disable_timing` constraints were specified for different cells with the same `-to` and `-from` options, only the first constraint was applied and the others were ignored. This behavior has been corrected.
1606506 | Filters did not display all clocks in the Timing Report Explorer. | Timing Report Explorer has been fixed to display all clocks in the clock filtering list for Min report.
1558211 | On Linux systems, the operating system was terminating the "mdrg5" and "smartsta" processes during Place & Route (P&R) and when launching SmartTime. | This issue has been addressed by reducing the peak memory consumption of SmartTime. The customer test case exhibited a very high number of logic levels. While memory usage has been reduced, it is still recommended to limit logic depth in designs to avoid excessive memory consumption.
1563635 | The TCL command for exporting IBIS files with the "Model Selector" option selected was not available. | An `-msel On|Off` argument has been added to the IBIS export TCL command to enable or disable "Model Selector" export option, resolving the issue.
1556802 | False Loss Lock indication was observed incorrectly in the Fabric CCC simulation. | Enhancement has been made in the SF2 Fabric CCC module, specifically in the PLL simulation model lock-loss generation functionality, resolving the issue.
1603020 | Additional arguments for Synplify Elite were being ignored. | For Synplify Elite/Premiere, user-provided additional arguments entered in the tool profile dialog box were not being passed to Synplify. This issue has been fixed, and the additional arguments are now passed as expected.
1613338 | The I/O couldn't be set to the desired pin in Libero, even though the pin appeared as available in the Constraint Manager and validated by DRC. | For the IOD TX Ratio 5 single-ended data output, the N side of the IOD pair is not available for use. This configuration requires both the P and N sides of the pair due to architectural overlay constraints. The TX_DATA overlay utilizes the IOD N (effectively consuming the F2I ports), rendering the IOD N unusable for other functions, including standard single-ended I/O. This requirement is clarified in Libero SoC v2025.2.
1648692 | The "Questasim ScintillaTk" package path was not configured in the Libero v2025.1 release installation. | New installation of QuestaSim has been packaged into Libero 2025.2 which resolves the issue.
1571301 | There were issues with PF_IO RX Delay RTL Simulation issue for RX delay taps greater than 125. | Support for narrow and wide mode delays in PF IODs has been provided.
1510223 | The Expose fractional clock parallel data was only available with fractional aligned mode, and not in the fractional dynamic mode. | Support has been added for the Expose fractional clock parallel data in the fractional dynamic mode as well.
01628141 01647372 | There were issues with the MSS LPDDR4 IBIS model generated using Libero SoC v2025.1 version. Without the "Model Selector" option, models were being exported for both input and output pins of BIDIR (Bidirectional) I/O. | Support has been added to export the model selector for BIDIR I/O's input side as well.
1543687 | The "CREATOR" field inside the STP file wrongly displayed FlashPro. | The "CREATOR" field inside the STP file has been updated to display Libero.
01622199 01625354 01652438 01645480 01666373 | The Libero SoC Design Suite was ignoring proxy settings on both Windows 10 and 11 systems. | The curl flags have been added to enable HTTPS proxy support, resolving the issue.
1585675 | Incorrect message was displayed in the programming log of the G4 devices. | The incorrect message has been removed and the issue resolved.
1616763 | SmartDebug displayed PCIe_bridge registers incorrectly. | The issue was caused by duplication of the PCIe bridge registers, which resulted in incorrect addresses being displayed. This has now been resolved, and the duplication has been prevented.
1571939 | The generated settings for PolarFire DLL in the PF_CCC configurator were incorrect in the "Phase Generation" mode. | The parameters have been updated in the configurator-generated netlist for the "Phase Generation" mode.
1572135 | RX-delay-line RTL simulation showed unexpected variations in effective TAP delays. | The PF IOD simulation model now supports 256 tap delays, increment/decrement by 1 tap delay and each tap provides 25 ps delay.
1637894 | The SDF writer incorrectly wrote zero delay for the RTG4 device family. | The SDF writer has been updated to bypass skipped pins and connect to the previous driving cells.
1589373 | Post synthesis generated netlist for the Synplify tool was incorrect. | The Synplify tool was incorrectly returning an integer instead of a real value when performing division where the numerator was a real number and the denominator an integer, as defined in the "std.vhd" library. This issue has been fixed in this release.
1556938 | SmartDebug was displaying incorrect write-leveling results. | The write-level tap delay value has been fixed by correctly reading the lower significant bits of the register.
01588834 01595754 | The relationship between DQS position and delay tap width in MSS DDR differed from that in Fabric DDR. | This issue resulted in a drift towards the left margins in the MSS DDR I/O margin. It has been resolved.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2025.2 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 1-3.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary | Resolution
--- | ---
MSS_DDR DQS position was not center-aligned for DDR3 and LPDDR3 for passing the DDR training. | The relationship between DQS position and delay tap width in MSS DDR differed from that in Fabric DDR, which resulted in a drift toward the left margins in the MSS DDR I/O Margin. This issue has now been resolved.
Libero GUI crashed when the MegaVault location was changed to /integ/tools/megavault/MegaVault_rr2_lin/. | The crash was caused by invalid syntax in the MegaVault structure. A check has been added to detect syntax issues early and prevent crashes for users.
There was issue with clock halt using Live Probe negative edge. | PolarFire now supports setting negative edge trigger on a Live Probe signal to halt the clocks.
PF_IOD_OCTAL_DDR core version 2.0.109 was failing at synthesis. | The tool now automatically generates all possible exception constraints (false paths).
Synthesizing design with CoreAHBLite was failing. | This issue has been resolved and synthesis passes with "ACP ON" on the Windows machines.
SynplifyPro mapping took 5 hours on simple designs. | This long runtime issue has been resolved and synthesis finishes faster.
For a valid RTL, Synplify incorrectly reported a warning. | This incorrect warning is no longer reported in the Synplify report.
The MPF200T-FCG784E part number should be added to the Silver license. | The license for this part number has been changed to be supported with a Silver license.
Internal assertion failed while running Place & Route. | The issue was caused by recent updates to the timing-cost function and occurred in ECO flows or designs containing many fixed instances. The problem has been resolved, and all designs pass successfully.
Incorrect Operating System information was reported in the `libero_setup_info.txt` file for the newer versions of Windows, like Windows 10 and 11. | A fix has been added to correctly identify the operating system and populate it accordingly.

Rev: 2025.2

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