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# 6.6 Migrating Designs to Libero SoC

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## 6.6.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2023.1. For more information about updating a core version, see section Updating a Core Version.

Table 6-2.Core Enhancements and Upgrades
Core | 2023.1 Version | Status | Comments
--- | --- | --- | ---
PF_DDR3 | 2.4.122 | Production | Add the CA/CK Additive Offset parameter option to the DDR Configurator.
PF_DDR4 | 2.5.111 | Production | Add the CA/CK Additive Offset parameter option to the DDR Configurator.
PF_INIT_MONITOR | 2.0.307 | Production | The core has been updated with default values to avoid simulation warnings.
PF_IOD_GENERIC_TX | 2.0.115 | Production | The core has been updated to resolve undefined output in simulation on `TXD` and `TXD_N` pins.
PF_QDR | 1.9.104 | Production | See section PF_QDR Reset.
PF_RGMII_TO_GMII | 1.3.108 | Production | Repackage PF_RGMII_TO_GMII with latest PF_IOD_GENERIC_TX for Libero SoC v2023.1.
PF_TX_PLL | 2.0.302 | Production | See section TX_PLL: Enable Tx Lane Alignment.
PFSOC_INIT_MONITOR | 1.0.307 | Production | The core has been updated with default values to avoid simulation warnings.

## 6.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right-click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.