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# 12.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2021.2 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 12-5.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Description | Resolution
--- | --- | ---
00967427 | For SmartFusion2 and IGLOO2 Libero designs, if the customer selected an eNVM component only in bitstream along with the sanitize all eNVM pages option, the output of Generate Bitstream, Export Bitstream, and Export FlashPro Express Job produces incorrect bitstream file where running ERASE action will program eNVM instead of sanitizing eNVM. | This issue is fixed in Libero v2022.2.
493642-2828855802 | Unused encryption keys (UEK2, UEK3) must be disabled in Key Mode Policy. | In the key Mode Policy UI check boxes for unused UEK2 and UEK3 (if UEK3 is supported for the device) are disabled and "off." When open existing designs with key mode policy set to "enable" for unused UEK2/UEK3 keys, the policy resets to disabled, programming tools that generate bitstream are invalidated, and the user is informed about changes and asked to re-run tools. Newly exported TCL scripts set UEK2/UEK3 key mode policy parameters to "false" (disabled) if the keys are not used. Existing TCL scripts that enable key mode policy for unused UEK2/UEK3 keys will error-out.
493642-2822456042 | Show SPI Flash client type in design initialization and data memory report. | The SPI Flash client type is shown in the report.
493642-2528026909 | PF: Document post-layout macros. | The Post-Layout macros are now documented in the PolarFire FPGA and PolarFire SoC FPGA Macro User Guide .
1-33183756 | `SD_SYN_ATTRIBUTES`: Need the ability to add a Synthesis Directive to a SmartDesign Component. | See section SmartDesign Enhancements
493642-2834448979, 493642-2838137518 | RTG4 FDDR fractional clock frequency not supported. | Fixed in RTG4FDDRC core version 2.0.102. Fixed in RTG4FDDRC_INIT core version 2.0.102. Fixed in FDDRC core version 2.0.101.
493642-2780872953 | `PF_CCC`: CCC configurator showing 3-digit accuracy, but actual accuracy is 2. | Updated configurator User Interface to allow for 3-digit accuracy.
493642-2709111900 | `PF_QDR`: Query related to DOFF signal in CoreQDR (`PF_QDR`). | Fixed in `PF_DQR` core version 1.8.203.
493642-2845898691 | PolarFire`IOD_GENERIC_RX` "expose fractional clock parallel data" port not working. | Fixed in `PF_IOD_GENERIC_RX` core version 2.1.104. `HS_IO_CLK` port connection issue has been resolved.
493642-2817010799, 493642-2838360828 | `PF_IOD_GENERIC_TX`: Add option to enable user control of clock pattern on `HS_CLK`. | Fixed in `PF_IOD_GENERIC_TX` core version 2.0.111.
493642-2836680172 | `PF_IOD_GENERIC_RX`: `IOD_GENERIC_RX` with fabric ratio of one generates the following constraints, which do not exist in the design. | Fixed in `PF_IOD_GENERIC_RX` core version 2.1.104.
493642-2813090173 | `RTG4_FCCCECALIB`: Use `CLK_50MHZ` for `APB_S_PCLK` when Dyn Config is enabled. | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
493642-2839029728 | `RTG4_CCC`: PLL with differential feedback. | Updated configurator User Interface to allow for dedicated pads to be configured in differential mode when using external feedback.
493642-2813090173 | `RTG4_FCCCECALIB`: RTG4 Enhanced PLL IP RTG4CCCECALIB SET mitigation. | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
493642-2811312932 | SDC processing is taking too much time for customer's design. |
493642-2654458589 | Support for `-start` and `-end` switches in `set_multicycle_path` constraint. | See section Timing Constraint Enhancements: Multi-cycle Start and End Options.
493642-2761382645 | SmartTime Apply filter is not working. | Apply filter activated in addition to stored filters.
493642-2859123557 | Different SmartTime behavior in Libero v12.3 and v12.6 for input delay constraint. | The path reported in the user set gives higher priority to fully constrained paths.
493642-2761427558 | Libero generated fdc file generates error during synthesis. | When a clock name (without get_clocks) contains a '/' don't convert the '/' to '.' into the fdc file for synthesis.
493642-2743715317 | Inconsistent behavior of SmartTime in Libero v12.3 and Libero v12.4. | SmartTime stops propagating clocks when a generated clock is reached, except when a generated clock is behind another generated clock with the clock source and the master pin.
493642-2805318705 | Differences between Design bitstream file type options while exporting FlashPro Express Job file and their impact on sNVM access. | The online help file for 'Include Plaintext Pass Keys' was updated to mention the differences between different design bitstream file types.
493642-2864361216 | Add instructions to install "lsb" library for running license daemons on Linux in addition to libc6-i386 (Ubuntu). | Added an instruction under Libero SoC Installation Instructions in Ubuntu for libraries to install.
493642-2706229069 | Correct the Tcl command report for timing in the user guide. | The Tcl Commands Reference Guide has been corrected for reporting inter-clock domain timing paths.
493642-2822285667 | Improve Libero message during DRC check. | Updated the Self-Instantiation description under Design Rules Check in online help.
493642-2816191143 | Error message correction needed. | Updated the error code message for error code `0x802B` in the FlashPro Express User Guide.
493642-2720279874, 493642-2724143412, 493642-2731049050, 493642-2729244859, 493642-2728846999, 493642-2730631859 | Synthesis fails in secure IP flow for Libero v12.2 and Libero v12.3. | Removed the unwanted commands in Libero SoC Secure IP User Guide.
493642-2835376443 | SET filter for `GRESET` is supported on dedicated I/O and fabric-routed signal. | The information about the GRESET macro was added to the RTG4 Macro Library User Guide.
493642-2829401262 | Chip Planner crashes after renaming the regions twice. | The crash has been resolved.
493642-2805280201 | Libero v12.5 SP1 I/O Editor: Pressing Enter key does not work. | This issue has been resolved; pressing the return key goes to the next cell.
493642-2608388565 | `SD_CONNECT`: `QUICKCONNECT`: Connecting modules using net names. | See section SmartDesign Enhancements.
493642-2863195365 | Exported SPI flash `.bin` file is unusable when programming SPI without Flash Pro Express. | This fixes an issue introduced in Libero SoC v2021.1 where the exported SPI Flash `*.bin` file was not useable by third-party solutions. Libero SoC v2021.2 exports SPI Flash images in raw format to allow for third-party use.
493642-2858675628 | SmartPower crashes in designs with RX only transceivers. | The fix avoids the crash when the transceiver is configured in RX-only mode.
493642-2779201786 | RTG4: Placement failure MSG for Enhanced CCC GLx connection needs improvement. | See section Dynamic CCC Placement Diagnostic.
493642-2810172350 | Memory required to run Driver Replication exceeds 16 GB. | Reduced memory consumption of Driver replication below 16 GB.
493642-2751002554 | `RTG4_FCCCECALIB`: Synchronize Release of `PLL_ARST_N` to `CLK_50MHZ`. | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
493642-2751002554 | `RTG4_FCCCECALIB`: Add timeout in `LOCK_WAIT` state. | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
493642-2694971261 | Device Info log displays wrong CheckSum and Design name in SPI Slave programming. | Issue resolved by inspecting both TX and RX busy bits of the SPI buffers.
493642-2812502249 | FlashPro6 support of W25Q128JWYIQ SPI memory device. | See section SPI Flash Programming Enhancements.
493642-2695952363, 493642-2698474573 | Support for Gigadevice flash memory. | See section SPI Flash Programming Enhancements.
493642-2858675628 | SmartPower crashes with PF RX-only XCVR. | The fix avoids the crash when the transceiver is configured in RX only mode.
493642-2848653939 | `SD_BIF: AXI4STREAM`: Generated VHDL from SmartDesign is illegal if an AXI-Stream port is marked unused. | Updated the AXI4 Stream Bus Interface definition to handle unused signals properly.
493642-2829905835 | `PF_CCC`: `PF_IOD_TX_CCC` Simulation Issue: unstable `PLL_LOCK` with cascaded CCCs. | PolarFire CCC simulation model updated to consider tolerable deviations at input reference clock of `PF_IOD_TX_CCC`.
493642-2825894420 | `PF_CCC`: PolarFire PLL external feedback differences between Libero SoC v12.4 and Libero SoC v12.5. | PolarFire CCC simulation model updated to return the input and output clock alignments as they behaved in Libero v12.4.
493642-2843193216 | `PF_TVS`: Simulation behavior. | PolarFire TVS simulation model updated to clear `TEMP_HIGH` and `TEMP_LOW` alarm flags by asserting `TEMP_HIGH_CLR` and `TEMP_LOW_CLR` inputs, respectively.
493642-2844075913 | `PF_XCVR`: 12.5G XCVR simulations are not working for PolarFire. | PolarFire XCVR simulation model updated to recognize change in `FBDIV` and relocks `TXPLL`.
493642-2761489068 | `PF_XCVR`: Simulation not working for SERDES PMA lanes through DRI. | PolarFire XCVR simulation model updated to access all XCVR lanes through DRI.
493642-2771746791 | `G4_XCVR`: `TX_CLK_STABLE` is not de-asserted in simulation when REF CLK is not available. | IGLOO2 XCVR simulation model updated to de-assert the `TX_CLK_STABLE` signal when ref clk input is stuck at one or zero other than regular clock behavior.
493642-2798868524 | `PF_XCVR`: Transceiver RX Ready is asserted and RX clock is toggling even when ``PCS_ARST_N`` is asserted in simulation. | PolarFire XCVR simulation model updated to de-assert `RX_Ready` and to stop `RX_CLK_R` clock when `PCS_ARST_N` is asserted.
493642-2796352746 | `PF_XCVR`: Simulation not working when Rx CDR Reference clock source is set to fabric in RX-only transceiver mode. | PolarFire XCVR simulation updated to work when the Rx CDR Reference clock source is set to fabric.
493642-2845474275 | `PF_CCC`: PolarFire CCC simulation issue. | PolarFire CCC simulation model updated to remove the misalignment between 0 and 180 phase shifted outputs.
493642-2739447777, 493642-2842563037 | `PF_CCC`: Incorrect simulations results on PolarFire CCC. | PolarFire CCC simulation model updated to generated accurate frequencies for certain configurations.
493642-2829954025 | `RTG4_LSRAM`: Dual Port LSRAM sim model warnings are incorrect or missing. | RTG4 LSRAM simulation model updated to print warning messages in case write collisions occurring on the same clock.
493642-2776910289 | `PF_DRI`: PolarFire reconfiguration controller. | PolarFire DRI simulation model updated to consider `PSTRB` input.
493642-2816191143 | Error message correction needed. | Libero/FlashPro Express now displays the correct message for signal integrity issues.
493642-2780147696 | Device info log should display Step Mark, firmware version. | `DEVICE_INFO` now shows Die Revision and Die Firmware Version, as requested.
493642-2663319510 | Incorrect BSR description on `SC_SPI_SDI` / `SDO` of SmartFusion2 and IGLOO2 BSDL file. | SmartFusion2 and IGLOO2 BSDL files now have correct descriptions for `SC_SPI_SDI` and `SC_SPI_SDO`.
493642-2855024392 | PolarFire: Print `TVS_MONITOR` status appropriately. | `DEVICE_INFO` now prints TVS status for each of the four channels only if its valid.
493642-2839083505 | Chain stp support. | Added support to export chain stapl that programs single Microsemi device in a JTAG chain.
493642-2777795242 | Differences in the power summary between the SmartPower and Power Estimator. | Changed IO static power model in Estimator to match the Smart Power IO power model
493642-2825236133 | Infer Gated Clocks from the Enabled-Registers option produce an incorrect netlist. | With the Gated Clock option set to ON, `UDRCLK` of UJTAG macro drives only one `CLKINT` in the instrumented design
493642-2791323207 | Synthesis error occurs when the keyword when is used as a keyword VHDL. | Synthesis passes when the keyword when is used in the condition to compare two signals or variables.
493642-2823251067 | Synplify crash on attached project (Libero v12.6). | SynplifyPro gives proper error message in the synthesis log file for the incomplete module header parameter list.
493642-2854862880 | Synthesis issue with customer design. | Crash has been resolved. Synthesis passes when all SystemVerilog files are ordered correctly through Libero.
493642-2749061712, 493642-2790763501, 493642-2793376084 | Compile fails. | Libero → Compile passes for the generated synthesis netlist. The new synthesis netlist has been updated to handle escape characters for the ports, instance and the net names.
493642-2759082638 | Libero archive project. | HDL Core definitions are now archived properly when selecting Project Files Only mode.
493642-2836226625 | Libero deletes the non-existent BIST parameters when TCL file is exported for SystemVerilog modules. | Fixed this issue to make sure that an incorrect list of params does not come from packages that are not related to the core. The exported TCL is now correct,
493642-2827333700 | Linked File issues with Libero v12.6. | Fixed the create_link function that was incorrectly detecting the link file as local file by matching the parent project path and is importing file locally.
493642-2782286269 | `PF_DDR`: Implement error message if required `IOSTD` for the DDR interface is not set. | Fixed the displaying of multi-line error text in the tool tip.
493642-2841223969 | PolarFire, PolarFire SoC, RT-PolarFire, RT-PolarFire SoC: Add support for LVDS18 input and output. | See section LVDS 1.8V GPIO Standard (LVDS18G).
493642-2856101322 | IGLOO2/RTG4_SERDES: Lock user to enter all `TX_AMP_RATIO` more than 0x80. | Added proper DRC to the configurator.
493642-2613190339 | SmartPower issues false warnings. | Warnings are removed because they were coming from an fabric element that has an IIP interface that connects to a clock that is not used.
493642-2831101105 | Enhancement: Alter the labels in the Manage Clock Domains dialog box. | The labels Available clock domains and Show the clock domains are altered in the Clock Domain dialog box.
493642-2851337659 | Hold time violation with custom volt/temp setting. | See section RTG4 Input Pad Performance Improvement.

Table 12-6.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Description | Resolution
--- | ---
PolarFire: SPI: add encryption status in the CDIDAM. | A new User Security column has been added to the SPI Flash clients table.
For PolarFire and PolarFire SoC, older core versions of `PF_DRI` core had a PCIe tab indicating that DRI could access PCIe registers. However, DRI is needed to access only the related XCVR lane used with a PCIe controller. | The latest version of PF_DRI v1.1.104 does not have the options to enable the PCIe DRI interface. Moreover, the Tcl parameters to enable the same have been removed from the core. Migration succeeds, but the old Tcl scripts must be updated to delete the corresponding Tcl parameters from the core configuration.
`SD_SYN_ATTRIBUTES`: Customer wants support for Synthesis Attributes added to Canvas. | See section SmartDesign Enhancements.
Add PolarFire Libero support for safety-critical applications. | See section Lock Bits Configuration and Enhanced Configuration Report for Safety-Critical Applications.
PolarFire: `PF_DRI` for PCIe. | Removed the PCIe tab in DRI configurator.
`G4_PCIE SERDES_IF`: Add warning when the PCIe AHBLite interface is selected. | See section Customer Advisory Notification: SmartFusion2/IGLOO2/RTG4 SERDES PCIe AHBLite Issue.
`PF_CCC` input frequency needs more significant figures. | Updated PF_CCC configurator User Interface to allow for 3-digit accuracy.
`PF_LPDDR3`: LPDDR3 needs to support issuing of self-refresh command. | Fixed in `PF_LPDDR3` core version 2.3.113. See section LPDDR3 Self-refresh Entry and Exit.
`PF_PCIE`: PolarFire support for 64-bit non-prefetchable BAR in PCIe EP. | Updated `PF_PCIE` configurator to add 64 bit non-prefetchable BAR option.
`RTG4_FCCCECALIB`: Change to `PLL_RST_N` input and configurable SYNC or ASYNC reset. | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
`RTG4_FCCCECALIB`: Supply NDC to turn on SET mitigation for each core instance. | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
`RTG4_CCC`: Increase significant figures allowed in CCC configuration GUI. | Frequencies can now be entered with 4-digit precision.
Cascaded CCC Clock Generation is 0 ns. | Fixed the clock generation when two generated clocks are cascaded and one of them is combinational.
`RTG4_FCCCECALIB`: Supply NDC to turn on SET mitigation for each core instance. | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
Missing path from bi-directional port with generated clock. | When searching for paths from a generated clock set on a bidirectional port, SmartTime looks for paths going out of the FPGA (as if the port was output only) as well as the paths coming into the FPGA.
FlashPro Express v12.3: `run_selected_actions` TCL command not generating return code. | The description of the TCL command`run_selected_actions` was updated to specify that the selected action does not return an exit code.
PTOLEMI EXCEPTION: Timing cell does not exist for `BANKEN_SE_ICBW`. | The timing model for the cell was missing from the timing database.
FlashPro 6: Support Micron MT25QL02G SPI-Flash. | See section SPI Flash Programming Enhancements.
Add a refresh button to GUI to rescan and reattach to FlashPro hardware. | Enhancement has been added.
SmartDebug RTG4 SERDES reports `RX_PLL` and `TX_PLL` unlocked on Dev Kit. | The appropriate `Rx_PLL` and `TX_PLL` values are now shown in the SmartDebug tool.
`PF_XCVR`: Inconsistency between hardware and Sim behaviors with RX PLL lock. | PolarFire XCVR simulation model updated to have correct behavior on `RX_IDLE`, `RX_READY`, and `RX_VAL` in simulations in absence of serial traffic.
`PF_CCC`: Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time <time> ps. | PolarFire CCC simulation model updated to stabilize internal signals before their use to avoid infinite iteration limits.
Enable SPI-Flash Programming using customer STAPL file attached to IGLOO2 device. | Fixed FlashPro Express to allow loading custom stp without device density/package, enabling customers to embed custom JTAG commands that will work on any device.
Onehot encoding flagged on a Synopsys provided VHDL library CD231: std1164.vhd"|Using onehot encoding for type mvl9plus. | If SynplifyPro encounters a `type` statement as below to declare a set of values, it gives a note even if the state machine is not synthesized. Type `MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error)`
Add date and time into `.prjx` to indicate when it was last used, saved, or modified. | Starting with Libero SoC v2021.2, a `libero_setup_info.txt` file is created in the Libero project directory and updated when the `.prjx` file is modified. For details, see the Libero SoC Design Flow User Guide .
`HDL_LANGUAGE`: HDLPLUS: `LINK_FILE`: HDLPlus definition on linked files is lost when design created on Windows is opened on Linux. | Libero SoC v2021.2 resolves this issue where HDL core using HDL links are corrupted when moving the project between Linux and Windows operating systems.
`HDL_LANGUAGE`: HDLPLUS:`LINK_FILE`: SmartDesign core definition gets corrupted with link loss. | Libero SoC v2021.2 resolves this issue where HDL core using HDL links are corrupted when moving the project between Linux and Windows operating systems.
SmartFusion2: MSSUBIT settings will not be correct if any LUT is placed at location (0,0). | Corrected reporting when LUT is placed at (0,0).
`PRPF_016`: Failed to automatically place instance 'PROC_SUBSYSTEM/pf_JTAG_Debug_0/pf_JTAG_Debug_0/genblk1.genblk1.genblk1.UJTAG_inst'. | The merging of multiple UJTAG macros failed when the Infer Gated Clocks from Enabled-Registers Synthesis option was used for the design. This issue has been resolved in Libero SoC v2021.2.

Rev: 2026.1

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