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# 12.5 New Silicon Features and Enhancements

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## 12.5.1 PolarFire, RT PolarFire, and PolarFire SoC

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### 12.5.1.1 Lock Bits Configuration and Enhanced Configuration Report for Safety-Critical Applications

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PolarFire, RT PolarFire, and PolarFire SoC devices allow you to restrict access to the Transceiver, PCIe, Transmit PLL, PLL, DLL, Lane Controller, Crypto, TVS, Tamper, and VoltageDetect configuration registers. Libero SoC v2021.2 includes the Register Lock Bits Configuration tool to lock these configuration registers and prevent them from being overwritten by initiators that have access to these registers.

An initial Configuration Lock Bit file is created when you generate FPGA array data. The file is named `<project>/designer/<design>/<design>_init_config_lock_bits.txt`. All registers or blocks are unlocked by default. Use this file as a template to make changes. Modify it to ensure that the lock bits are set to 0 for all register bits you want locked, and then save the file with a different name.

To import the Lock Bit Configuration File into a project:

1. From the Design Flow window, click Configure Register Lock Bits.
2. Click the Browse button, go to the text file that contains the Register Lock Bit settings, and import the file into the project.

Note: Simulation support for this feature is unavailable.

For more details, see the AC478: PolarFire FPGAs for Safety-Critical Applications.

### 12.5.1.2 Power Up to Functional Timing (PUFT) Data

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Libero SoC v2021.2 adds information about Power Up To Functional timing (PUFT) data in the Design Initialization Data and Memories report. To indicate the completion of initialization of each block (PCIe, XCVR, and RAM), a signal is asserted as part of device initialization after power-up. For example, the `PCIE_INIT_DONE` signal is asserted after all the PCIe-related registers are configured. The `DEVICE_INIT_DONE` signal from`PF_INIT_MONITOR` is the last signal asserted.

For more details, see the PolarFire FPGA and PolarFire SoC FPGA Device Power-Up and Resets User Guide.

### 12.5.1.3 LVDS 1.8V GPIO Standard (LVDS18G)

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Libero SoC v2021.2 introduces a distinct I/O standard called LVDS18G to support LVDS I/Os on GPIO banks with VDDI set to 1.8V.

For more details, see the following documents:

- PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide
- PDC Commands User Guide for PolarFire FPGA

### 12.5.1.4 User Control of Output Clock Port Pattern on IOD Generic Transmit Interface

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Libero SoC v2021.2 adds an option to enable user control of the output clock port (`HS_CLK`) pattern on the `PF_IOD_GENERIC_TX` interface.

For more information, see the PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.

### 12.5.1.5 LPDDR3 Self-refresh Entry and Exit

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Libero SoC v2021.2 adds the capability of self-refresh entry and exit to LPDDR3.

For more details, see the PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.

### 12.5.1.6 `PF_QDR DOFF_N` Port and Fast Simulation Enhancements

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Libero SoC v2021.2 adds an option to Export DOFF_N Port and enables fast simulation with the latest version of `PF_QDR`.

For more details, see the PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.

### 12.5.1.7 SPI Flash Programming Enhancements

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Libero SoC v2021.2 adds the following capabilities to SPI Flash programming.

- Support for loading STAGE3 initialization client when adding SPI Bitstream client in SPI Flash. Support for exporting STAGE3 file along with SPI bitstream file in the Export Bitstream dialog box.

- Support for loading binary image (`.bin`) SPI Flash clients.
- Programming support of Gigabit SPI Flash devices: GD25S512 and GD25Q256.
- Programming support of Micron MT25QL02G SPI Flash device.
- Programming support of Winbond W25Q128JWYIQ SPI Flash device.

For more information, see the Libero SoC Design Flow User Guide .

### 12.5.1.8 PolarFire XCVR-Sourced Fabric Clocks and Jitter Compensation

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The PolarFire XCVR can source three different clocks into the fabric:

- `TX_CLK`
- `RX_CLK`
- `REFCLK` (`FAB_REF_CLK`)

These clocks contain high-frequency jitter that is not automatically considered by Libero in the timing report and SmartTime. It is recommended that users add clock-uncertainty constraints to these clocks in their design. The following table shows recommended values for clock uncertainty per clock, resource, and speed-grade.

Table 12-3.Recommended Values for Clock Uncertainty
Clock Type | STD | -1
--- | --- | ---
`FAB_REF_CLK` on Global | 275 ps | 200 ps
`FAB_REF_CLK` on Regional | N/A | N/A
`TX_CLK_G` on Global | 300 ps | 225 ps
`TX_CLK_R` on Regional | 225 ps | 150 ps
`RX_CLK_G` on Global | 325 ps | 250 ps
`RX_CLK_R` on Regional | 250 ps | 175 ps

The following example shows a clock-uncertainty constraint that uses a -1 speed grade.

    set_clock_uncertainty -setup 0.150 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_R } ]

    set_clock_uncertainty -setup 0.175 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_R } ]

The following example shows a clock-uncertainty constraint with STD speed grade.

    # TX_CLK and RX_CLK on Globals

    set_clock_uncertainty -setup 0.300 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_G } ]

    set_clock_uncertainty -setup 0.325 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_G } ]

    # FAB_REF_CLK on Global

    set_clock_uncertainty -setup 0.275 [get_clocks PF_DDR4_C0_0/CCC_0/pll_inst_0/OUT1]

The automatic management of these constraints will be added in a future release of Libero SoC.

Note: It is also important to add the other required jitter sources as clock uncertainty into your design constraints. See the datasheet for the jitter to be added for components such as PLL, DLL, and RC Oscillator. For input pins that are direct or are inputs to the DLL (but not for a PLL), the input jitter on the clock input pin must also be added to your timing constraints.

## 12.5.2 PolarFire SoC

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### 12.5.2.1 Standalone MSS Configurator Enhancements

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Libero SoC v2021.2 extends the PolarFire SoC standalone MSS configurator with the following enhancements:

- An option to have both SD and eMMC I/Os pre-configured if dynamic reconfiguration is needed by the application
- Package pin information for RefClk, DDR and SGMII I/Os added to the MSS configurator report
- An option to have the eMMC and CAN clock sourced from the fabric (production devices only).

For more information, see the PolarFire SoC MSS Configurator User Guide

## 12.5.3 RT PolarFire

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### 12.5.3.1 Design-Specific IBIS Models

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Libero SoC v2021.2 adds the ability to generate design-specific IBIS models for RTPF500T/TS/TL/TLS devices.

## 12.5.4 RTG4, SmartFusion2, and IGLOO2

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### 12.5.4.1 Dynamic CCC Placement Diagnostic

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Libero SoC v2021.2 adds a diagnostic table of recommended pin assignments to guide you out of Dynamic CCC placement failures in RTG4, SmartFusion2, and IGLOO2 designs.

For more details, see the UG0586 - RTG4 FPGA Clocking ResourcesFPGA Clocking Resources User Guide.

## 12.5.5 SmartFusion2 and IGLOO2

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### 12.5.5.1 Secure Production Programming Solution Key Rotation Flow

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Libero SoC v2021.2 adds the ability to securely update/rotate keys in Secure Production Programming Solution (SPPS) flows for SmartFusion2 and IGLOO2 devices.

For more details, see the Job Manager User Guide .

## 12.5.6 RTG4

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### 12.5.6.1 RTG4 Input Pad Performance Improvement

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Libero SoC v2021.2 includes an update to the RTG4 Input pad timing model to improve an over-conservative timing margin. Prior to Libero SoC v2021.2, false violations may occur making timing closure more difficult. With this update, such false violations will be removed. Minor performance improvement may also be seen. No action is required for completed designs that have met timing across all corners. Ongoing or new designs are recommended to upgrade to Libero SoC v2021.2.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.