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# 3.5 New Silicon Features and Enhancements

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## 3.5.1 PolarFire, RT PolarFire, and PolarFire SoC

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### 3.5.1.1 Phase Direction Parameter for BCLK/SCLK Alignment

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Libero SoC v2024.2 adds support to PF_IOD_GENERIC_RX/PF_IOD_TX_CCC core to generate the COREBCLKSCLKALIGN component within the RX_IOD component. A new dynamic training direction parameter BCLK/SCLK alignment has been added as part of this change. This option supports both Forward and Backward modes and is user configurable as “Phase Direction.” The IOD configurator sets “Backward” phase direction as the default.

### 3.5.1.2 “CK/CA additive offset” Parameter in the Training IP of DDR Controllers

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Libero SoC v2024.2 has PF_DDR3 and PF_DDR4 cores that support a “CK/CA additive offset” parameter. This parameter is added to the cores’ training IP of the DDR controllers and ensures that no unnecessary warnings are generated during the training phase. As a result, the port ADDR_VCOPHS_OFFSET_CFG_INIT value can now be changed based on the CK/CA additive offset from the user interface.

### 3.5.1.3 Project Setting Default I/O Technology LVCMOS 3.3V

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Libero SoC v2024.2 adds I/O standard support for TRIBUFF_DIFF and BIBUF_DIFF differential I/Os for 3.3V default I/O technology by selecting an appropriate I/O standard. When this is set within Libero settings, the default IO STD for TRIBUFF_DIFF and BIBUF_DIFF I/Os always shows as LVPECLE33.

### 3.5.1.4 FlashPro 6: SPI-Flash Programming Support for ISSI Flash Memory

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Starting with Libero SoC v2024.2, FlashPro 6 has been enhanced with programming support for IS25WP256D-JLLE.

Rev: 2025.2

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