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# 1.6 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero® SoC v2026.1 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 1-1.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Summary | Resolution
--- | --- | ---
01548618 | Support was requested for newer Ubuntu versions with Libero® SoC. | The following Ubuntu versions are now supported with Libero: 22.04.3 LTS 24.04.3 LTS See the Platform OS Updates section for more information.
01551651 | CFG macro INIT strings were not visible in the Netlist Viewer. | The Netlist Viewer has been updated to display INIT strings for CFG macro instances. Users can now right-click a CFG macro and select "Get Init Params" to view the macro’s INIT string. See the Netlist Viewer Displays CFG Macro Initialization Strings section for more information.
01552158 | Synthesis failed with error: “Couldn't find binding for variable p”. | This compile error has been resolved and synthesis now passes successfully.
01566000 | An internal error occurred in `c_vhdl.exe` of the Synthesis tool. | The crash has been resolved. The synthesis tool now reports appropriate error messages.
01605468 | Incorrect feedback mux removal messaging was reported during synthesis optimization. | The incorrect “CL282” message has been corrected to report the appropriate synthesis message.
01634664, 01631506 | Error and warning codes had inconsistent descriptions in OEM_Message_Reference documentation. | The documentation has been updated to correct the descriptions for warning codes “CG238” and “CG100”.
01638904, 01637345 | Help documentation for the `syn_redhardlevel` attribute limitation was missing. | Help documentation has been updated to include the `syn_redhardlevel` attribute limitation.
1590754.0 | An m_generic issue was observed with the Synplify Pro version bundled with Libero SoC v2024.2. | The crash has been fixed, and the COREAXI4INTERCONNECT IP core has been updated to resolve the RTL errors. Synthesis now passes successfully.
01596808, 01604528 | Support was requested for Ubuntu 24.04 including running the PolarFire® SoC MSS Configurator on the latest Ubuntu versions, as Ubuntu 20.04 was approaching end of support. | Ubuntu 24.04.3 LTS is now supported with Libero SoC and PF Studio, with required runtime dependencies installed using the provided `check_linux_req.sh` script. MSS generation has been verified in both GUI and batch mode for standalone MSS and MSS from Libero. See section Platform OS Updates section for more information.
01626076 | Updates were requested for I/O standard and drive-strength handling on reserved pins for RTG4™ devices. | The layout log now prints the I/O settings for the reserved PROBE_READ_DATA output pin when selected. For more information, see the PROBE_READ_DATA Pin section.
01660477 | The I/O Editor displayed drive impedance values in milliamps instead of ohms. | The configured MSS DDR impedance value is now displayed in ohms in the new MSS Impedance (Ohm) column, correctly distinguishing impedance (ohms) from output drive (mA). See the MSS DDR Impedance Display in Ohms section.
01768254 | The Device Selection table did not show 24 transceiver lanes for RTPFS460ZT/ZTS/ZTL/ZTLS devices. | The Device Selection table under "Project Settings" has been corrected to show 24 transceiver lanes for all RTPFS460ZT/ZTS/ZTL/ZTLS devices in the CG1509 and FC1509 packages. This change updates the displayed lane count only and has no impact on any design flow.
01650912 | “Undo” behavior was inconsistent in Libero SoC. | The "Undo" and "Redo" behaviors have been corrected to operate consistently in the Libero SoC text editor.
01656398 | PF_IOD_GENERIC_RX calculated I/O clock speed and fabric clock speed incorrectly when the data rate was entered as a whole number without a decimal point. | The PF_IOD_GENERIC_RX configurator has been updated to handle data-rate values consistently whether they are entered with or without a decimal point. For more information, see the PF_IOD_GENERIC_RX Data Rate and Fabric Clock Configuration Guidance section.
01674213 | DDR4 memory training time reported in SmartDebug differed from the actual measured training time. | SmartDebug DDR4 memory training-time reporting has been corrected to use the user (fabric) clock as the reference instead of the memory clock, aligning the reported training time with the actual measured value.
01749194 | An issue was observed with PolarFire SmartDebug Eye Monitor. | SmartDebug behavior for Signal Integrity (SI) settings in the Eye Monitor has been clarified. Because SI settings cannot be read back from the device, SmartDebug loads either the user-configured settings or the settings modified in the previous session, and a pop-up message now informs the user of this behavior when a modified lane is selected.
01687724 | RTG4 programming options required updates in the tool UI and Tcl command flow | System Controller Suspend Mode is now available as a project setting. The Programming Bitstream Options UI and related Tcl command have been updated accordingly. For more information, see the System Controller Suspend Mode (SCSM) and One-Time Programmable (OTP) sections.
01695557 | A bitstream generation message was requested for the RTG4 System Controller Suspend Mode enhancement. | Bitstream generation now displays a warning when System Controller Suspend Mode is disabled, helping users confirm the setting before generating programming files. For more information, see the System Controller Suspend Mode (SCSM) section.
01690337 | MSS DDR Debug DQ/DQS optimization displayed incorrect stage results and parameters. | The MSS DDR Debug pass/fail determination has been corrected to use the appropriate training-status registers, so DQ/DQS optimization stage results and parameters are now reported correctly.
01700330 | SmartDebug tool crashed on Ubuntu 22.04. | The SmartDebug crash on Ubuntu has been resolved. The tool now launches and operates correctly when used with the Embedded FlashPro programmer on Ubuntu
01690844 | The Parameter Report displayed an empty instance name when multiple top modules existed. | The Parameter Report generation has been corrected so that an empty instance-name entry is no longer produced when multiple top modules are present in the project.
01695547 | Libero Build Hierarchy could hang when a VHDL function type mismatch was present. | Libero now reports the VHDL error instead of hanging during Build Hierarchy when a VHDL function type mismatch (for example, mixing real and integer types) is present.
01708923 | HDL core recognition was inconsistent in the Libero SoC design hierarchy. | HDL core recognition has been corrected. A parameterized module added via a Tcl script (using create_links) and converted to an HDL+ core is now consistently recognized as an HDL+ core in the Design Hierarchy and instantiated correctly in SmartDesign.
01718510, 01734432 | Support was requested for adding a plain-text data client in eNVM as well as data client in eNVM concurrent with Boot Mode-2 client in sNVM. | Plain-text data client support has been added in eNVM. For more information, See the eNVM Configuration section.
01736313 | HDL+ incorrectly generated parameters when a SystemVerilog import statement was present with MiV_RV32. | HDL+ parameter extraction has been updated to import only parameters explicitly imported in the source file. Parameter extraction now supports wildcard imports and extracts only explicitly specified parameters for named imports.
01742180 | Place-and-route failed for an RTPF TSN design involving global signals driving wide mux structures. | Routability has been improved for designs where global signals drive wide-mux structures, reducing routing conflicts and allowing the affected design to complete place-and-route. See the Routability Improvements section.
1646619 | Enhancement was requested for the PF_Crypto core configurator. | The PF_Crypto tooltip and parameter-description guidance have been updated to clarify the supported AHB clock frequency ranges. The embedded DLL must be enabled for AHB clock frequency ≥ 125 MHz and disabled for ≤ 70 MHz. Frequencies between 70 MHz and 125 MHz are not supported. The fix is available in PF_CRYPTO 1.0.111. See the PF_Crypto AHB Clock Frequency Guidance section for more details.
811815 | PF_IOD back-annotated simulation included external timing checks on IOG/LANECTRL for dynamic IOD configurations without external timing check arcs. | IOD/LANECTRL external check arcs are filtered out from the back-annotated SDF. This update is part of PF_IOD back-annotated functional simulation support.
1669714.0 | QuestaSim 2024.3 in Libero SoC v2025.1 experienced a 120-second startup delay in air-gapped environments. | The QuestaSim startup behavior has been improved to avoid the observed delay in air-gapped environments.

Table 1-2.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary | Resolution
--- | ---
The default value of the PFSoC MSS `BFM_SELECT` parameter required an update. | The default value of the PFSoC MSS `BFM_SELECT` parameter has been updated from `1` to `0`.
QuestaSim experienced a startup delay in air-gapped environments. | The QuestaSim startup behavior has been improved to avoid the observed delay in air-gapped environments.
IBIS output contained zero RLC values for selected RTPFS460ZTL/FC1509/MIL and MPF300XT configurations. | IBIS model generation has been corrected to generate valid RLC values for the affected device/package configurations.
MSS I/O IBIS generation reported an unknown model error for an LVCMOS25 configuration. | MSS I/O IBIS model generation has been corrected so the affected LVCMOS25 model is generated and referenced properly.
Some models were missing in PFSoC IBIS generation runs. | PFSoC IBIS generation has been updated to export the required models in generated IBIS files.
Additional guidance was needed because UL_DEBUG Lock does not block debug through the exposed MSS JTAG fabric interface. | An informational message has been added to clarify debug access behavior when UL_DEBUG Lock is used with the exposed MSS JTAG fabric interface.
Enhancements were requested for the SPI Configurator. | The SPI Configurator has been enhanced to improve supported configuration workflows.
System Controller Suspend Mode required additional changes and enhancements. | System Controller Suspend Mode handling has been updated with additional logs, warnings, and improved UI. For more information, see the System Controller Suspend Mode (SCSM) and One-Time Programmable (OTP) sections.
Probe settings in the Configure Programming Options dialog could not be changed after constraints probe settings were applied. | Probe settings handling has been corrected so programming option changes can be applied as expected.
Changes made to IOPADP_IN and IOPADN_IN in the previous release required correction. | The SDF was updated to move the IOPADN_IN arc delay to IOPADP_IN.
Physical Memory Protection configuration in PFSoC MSS was missing required DRC checks. | Additional DRC checks have been added to validate Physical Memory Protection configuration settings. For more information, see the PMP Configuration DRCs for Batch Mode section.
SmartDebug SI setting changes were not retained after applying user-configured values and importing a PDC file. | SmartDebug SI settings handling has been corrected so modified values are retained after applying settings and importing PDC files.
Libero® crashed when viewing or exporting the memory map. | Memory map view and export handling has been corrected to prevent the crash.
Block flow compile could fail for designs with long instance, net, or port names. | Libero SoC v2026.1 increases name-length handling in block flow, including support for port names up to 1024 characters, preventing compile crashes for affected RTG4™, PolarFire®, and PolarFire SoC designs.
During JTAG programming for PolarFire SoC/PFSoC devices, the configured I/O state for some pins could be applied incorrectly. For example, pin G17 could remain at logic 1 even when configured to logic 0. | The I/O State configuration file has been corrected to fix the BSR pin order for PFSoC devices, ensuring configured I/O states are applied correctly during programming.

Rev: 2026.1

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