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# 10.6 Migrating Designs to Libero SoC 2021.3

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## 10.6.1 Core Enhancements and Upgrades

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The following table lists the core enhancements and upgrades. For more information about updating a core version, see section Updating a Core Version.

Core | 2021.3 Version | Status | Comments
PF_DDR4 | 2.5.103 | Production | Removed limit on DDR4 max speed for RT PolarFire devices.
PF_INIT_MONITOR | 2.0.205 | Production | Information about I/O Banks was missing for certain die/packages. This is fixed in this release.
PF_IOD_GENERIC_RX | 2.1.106 | Production | The Enable delay line simulation option is added to simulate early and late flags. Corrected component preview for Fractional Dynamic displayed in the Symbol view.
PF_IOD_GENERIC_TX | 2.0.113 | Production | Corrected differences between configurator’s Symbol view and the generated component view.
PF_IOD_OCTAL_DDR | 2.0.103 | Production | See section PolarFire, PolarFire SoC, RT PolarFire – Octal PHY Differential DQS Output.
PF_PCIE | 2.0.106 | Production | If the `DRI` and `RX` input pins are unused, they are tied-off correctly.
PF_RGMII_TO_GMII | 1.3.104 | Production | Repackaged this core with latest `PF_IOD_GENERIC_RX` and `PF_IOD_GENERIC_TX` cores.
PF_SYSTEM_SERVICES | 3.0.101 | Production | See section eNVM System Service.
PF_TAMPER | 1.0.203 | Production | See section PF_TAMPER SECURITY_LOCKDOWN.
PF_XCVR_ERM | 3.1.200 | Production | See section XCVR ERM Enhancements to Improve Transceiver Robustness.

## 10.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Update Component Version. The component will be automatically regenerated.
   1. Note: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. Also, the selected core version will be automatically downloaded from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right click on the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance and connect them or tie them off as needed, and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.