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# 11.2 Customer Notification (CN) Support

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Libero SoC v2021.2 includes changes that address certain important issues.

## 11.2.1 CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core

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With Libero SoC v2021.2, the RTG4 FCCC with Enhanced PLL Calibration core will be updated to improve robustness in various user configurations. The following changes are being implemented:

- Update the `PLL_ARST_N` input to `PLL_RST_N` and default to synchronous relationship with `CLK_50MHZ`, with a user option to revert to asynchronous assertion.
- Add `PLL_RST_N` reset release synchronization to ensure that reset release is always synchronous to `CLK_50MHZ`.
- Convert all resets internal to the PLL calibration soft IP into synchronous resets.
- Add synthesis directives to preserve/keep the PLL calibration soft IP's FSM state register and illegal state detection logic.
- Enable Single-Event Transient (SET) mitigation for all Flip-Flops (FFs) in each core instance via a Netlist Design Constraint (`.NDC`).
- When user dynamic configuration is enabled, drive the APB configuration interface with `CLK_50MHZ` input and remove option for a separate, user-supplied `APB_S_PCLK` input.
- Add a 500us timeout counter on the PLL calibration soft IPs `LOCK_WAIT FSM` state.

For more information, see CN19009C.

## 11.2.2 Customer Advisory Notification: SmartFusion2/IGLOO2/RTG4 SERDES PCIe AHBLite Issue

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In SmartFusion2, IGLOO2, and RTG4 families, under specific PCIe traffic patterns, SERDES PCIe AHBLite master interface to fabric functions improperly, requiring design conversion to an AXI-based SERDES PCIe configuration with a new FPGA fabric-based AXI-to-AHBLite bridge soft IP.

- An issue was discovered when using the AXI-to-AHBLite master bridge inside the PCIe block of the SERDES.
- Under specific PCIe traffic conditions, the AXI-to-AHBLite master bridge embedded within the SERDES block does not load its burst counter properly, which results in early burst completions.
- Subsequently,the PCIe transaction layer packet (TLP) logic generates incorrect read completion TLPs which will eventually result in the termination of the PCIe read TLP completions. The system behavior during this scenario depends on the root port used.

Traffic conditions known to cause this issue include:

- Write transactions with open read transactions.
- Read transactions with open write transactions.

For more information, see JAON-08OHTZ048.

## 11.2.3 CYER-05NWLS164: PolarFire Timing Data Update

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This customer notification applies to FPGA Static Timing Analysis (STA) data used with Microchip's PolarFire FPGAs. As part of continuous improvement efforts, Libero SoC v2021.2 has been updated to improve the accuracy of the PolarFire timing data in two specific cases, described in the following section.

Prior to Libero SoC v2021.2, the two PolarFire timing paths below used delay values that were slightly underestimated.

- Unused IP Interface Logic Elements used as regular combinatorial logic elements have LUT4 B input to Y output delay that was underestimated by up to 35 ps worst-case. IP Interface Logic Elements are used to connect hard IP blocks in the FPGA fabric, such as RAMs and Mathblocks, to user logic. When the associated hard IP blocks are unused in a design, Libero SoC can re-use the IP Interface LUTs and SLEs for user fabric logic. In this scenario, the 4-input LUT input B to output Y path can be used for user logic.
- Mathblock input registers have enable pin setup time that was underestimated by up to 77 ps worst-case. Examples of Mathblock input register enable pins are `A_EN`, `B_EN`, `C_EN`, and `D_EN`.

For more information, see CYER-05NWLS164.

Rev: 2025.2

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