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# 13.6 Migrating Designs to Libero SoC

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## 13.6.1 Core Enhancements and Upgrades

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The following table lists the core enhancements and upgrades.

Table 13-2.Core Enhancements and Upgrades
Core | 2021.1 Version | Status | Description
--- | --- | --- | ---
CORERXIODBITALIGN | 2.2.100 | Production | SmartDebug I/O Tap Delays.
`PFSOC_INIT_MONITOR` | 1.0.205 | Pre-production | Fixed synthesis error because of floating AND gate.
`RTG4_SRAM_AHBL_AXI` | 1.0.117 | Production | Made change to not expose Port-B Side of ECC signals when using USRAM option.
SmartFusion2/IGLOO2 TPSRAM | 1.0.102 | Production | Added support for initializing memory files through TCL.
SmartFusion2/IGLOO2 DPSRAM | 1.0.102 | Production | Added support for initializing memory files through TCL.
SmartFusion2/IGLOO2 URAM | 1.0.102 | Production | Added support for initializing memory files through TCL.
PF_RGMII_TO_GMII | 1.3.102 | Production | Repackaged with latest `PF_IOD_GENERIC_RX` and `PF_IOD_GENERIC_TX` core versions.
`PF_QDR` | 1.8.105 | Production | `PF_QDR`: `CoreQDR` BFM simulation: X observed during read for upper addresses.
`PF_INIT_MONITOR` | 2.0.204 | Production | Fixed synthesis error due to floating AND gate.
`PF_IO` | 2.0.102 | Production | Separate register mode for input/output/oe.
`PF_IOD_GENERIC_TX` | 2.0.109 | Production | The `PF_IOD` GUI does not allow non-integer frequencies.
`PF_IOD_OCTAL_DDR` | 2.0.102 | Production | `PF_IOD_OCTAL_DDR` configuration issues.
`PF_IOD_GENERIC_RX` | 2.1.102 | Production | The `PF_IOD` GUI does not allow non-integer frequencies.
`PF_XCVR` (Hidden) | 2.1.101 | Production | Incremental DFE support.
`PF_LPDDR3` | 2.3.112 | Production | Add a field to the LPDDR3 Configurator GUI to select the PLL Offset value.
`PF_DDR4` | 2.5.102 | Production | DDR4 - QoR - Throughput enhancement (bank group interleaving).
`CORESMARTBERT` | 2.8.101 | Production | No functional change. Repackaged with `PF_XCVR` v2.1.101. RN and HB were updated in `CoreSmartBERT` v2.8.101 compared to `CoreSmartBERT` v2.8.100.
`PF_XCVR_ERM` | 3.1.107 | Production | Incremental DFE support.

For more information about updating a core version, see Updating a Core Version.

## 13.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Replace Component Version.
3. Regenerate the core.
4. Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2026.1

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