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# 11.6 Migrating Designs to Libero SoC 2021.2

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## 11.6.1 Design and Core Invalidation

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### 11.6.1.1 RTG4FCCCECALIB Design Invalidation

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RTG4FCCCECALIB designs performed with earlier Libero SoC versions will be invalidated when Libero SoC v2021.2 is invoked.

- `Error: RTG4 CCC instances listed below must be updated to RTG4FCCCECALIB core v2.2.005 or later and regenerated. For more information about this requirement, refer to RTG4 Customer Notification CN19009C on the Microchip website.`
- `INFO: Converted design '...' to pre-Synthesize state because it contains RTG4 CCC instances that must be updated. Please check the log for more information.`
- `INFO: Converted design '...' to pre-Compile state because it contains RTG4 CCC instances that must be updated. Please check the log for more information.`

## 11.6.2 Core Enhancements and Upgrades

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The following table lists the core enhancements and upgrades. For more information about updating a core version, see section Updating a Core Version.

Table 11-4.Core Enhancements and Upgrades
Core | 2021.2 Version | Status | Comments
--- | --- | --- | ---
PF_DRI | 1.1.104 | Production | Removed the PCIe tab in the PF_DRI configurator. For information about how to reconfigure dynamically the PCIe configuration regiseters, see the PolarFire PCIe User Guide.
PF_IO | 2.0.104 | Production | The interface was corrected when configuring input and output register modes differently.
PF_IOD_GENERIC_RX | 2.1.104 | Production | Fixed issue when using the option to expose fractional clock parallel data port. Previously, `IOD_GENERIC_RX` with a fabric ratio of 1 generated false path constraints that did not exist in the design. These constraints have been removed. Exposes`eye_width_monitor` port with`RX_DDRX_B_G_A` configuration.
PF_IOD_GENERIC_TX | 2.0.111 | Production | See section User Control of Output Clock Port Pattern on IOD Generic Transmit Interface.
PF_IOD_TX_CCC | 1.0.122 | Production | Repackaged with latest core version of `PF_CCC`.
PF_LPDDR3 | 2.3.113 | Production | See section LPDDR3 Self-refresh Entry and Exit.
PF_QDR | 1.8.203 | Production | See section `PF_QDR DOFF_N` Port and Fast Simulation Enhancements.
PF_RGMII_TO_GMII | 1.3.103 | Production | Repackaged with the latest core versions of `PF_IOD_GENERIC_RX` and `PF_IOD_GENERIC_TX`.
RTG4FCCCECALIB | 2.2.005 | Production | See section CN19009C: Improvements to RTG4 FCCC with Enhanced PLL Calibration Core.
RTG4FDDRC | 2.0.102 | Production | Enables fractional clock frequency.
RTG4FDDRC_INIT | 2.0.102 | Production | Enables fractional clock frequency.
SmartFusion2/IGLOO2 FDDRC | 2.0.101 | Production | Enables fractional clock frequency.

## 11.6.3 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking on the core component in the design hierarchy and selecting Replace Component Version.
3. Regenerate the core.
4. Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

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