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# 2.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2025.1 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 2-2.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Summary | Resolution
--- | --- | ---
129520 | After having constrained the output path with QDR Chip Setup / Hold and skew requirements, Libero layout could not find valid timing windows. | A calculated tightening of the derating for specific IOPADs allowed an improvement of QDR slack: OCV deratings tightened based on Monte-Carlo Spice simulations. Silicon to software derating tightened to account for IOPAD specificity (large drivers and wires). Deratings limited to HSTL12/HSTL15 output pad (QDR) and LVDS25 output pad (SpaceWire).
140419 | There was optimization issue for `-ignore_clock_latency` timing constraint. | When using set_max_delay -ignore_clock_latency, Place and Route ignores the clock path, and tries to minimize the placement for the data path.
141172 | The report incorrectly referenced timing as relative to the assertion of `FPGA_POR_N` signal, which is an active-low signal. The report provided a single PUFT-related timing value without clarifying whether it represents the minimum, maximum, or typical value | The PUFT timing numbers in the Libero Reports have been enhanced and the message related to PUFT timing numbers has been updated.
141478 | Different edges were chosen for setup and hold analysis when recompiling the same design without modifications. | An ambiguity has been removed in multicycle calculation when -start is used with -setup and -hold but with a different set of anchors.
141222 | Incorrect clock edges were generated for hold analysis with -invert switch. | The -invert switch is used to correctly select the generated clock edges.
141198 | Incorrect master clock was observed when clocks were muxed. | The issue has been fixed during clock propagation where a clock continues past another clock source.
141197 | Incorrect information was observed in the CDC report for muxed clocks. There was an issue in the search for common ancestors in the CDC report that reported safe CDC as unsafe. | The issue has been fixed and such scenarios are now properly reported as safe.
140822 | Verify timing crashed when a timing constraints file was supplied with 'create_generated_clock' missing all of the parameters divide_by / multiply_by or edges. | Validation has been added to the timing constraints to ensure divide_by / multiply_by or edges is included as a parameter.
140867 | PF_IO: Libero v2024.2 has unconnected macros in PF_IO TRIBUFF / BIBUFF configuration. | The issue has been fixed.
140770 | When connected to IOD interfaces, IOPADN:D and IOPADN:E were floating. | IOPADN:D and IOPADN:E are no longer floating and are now connected to their respective IOPADP:D and IOPADP:E pins for outbuf, tribuf and bibuf diff macros, if connected to IOD interfaces.
137818 | DDR simulations were failing due to Questasim optimization in Questasim ME Pro 2024.2 version. | This is now fixed in Questasim ME Pro 2024.3 version.
140667 | An internal error in c_ver.exe occurred in SynplifyPro V202309M (Libero 2024.1) resulting in synthesis failure. | This is now fixed in SynplifyPro V-2023.09M-5 version.
140977 | Output generation delay was specifically observed when both clock and reset signals were toggled at same time. | PF_CLK_DIV simulation model has been updated to resolve the delay in Output clock Generation after reset is asserted back.
140911 | 3mA out drive as an option for SUBLVDS25 and SUBLVDS33 GPIOs was missing. | 3mA out drive has now been added as an option for SUBLVDS25 and SUBLVDS33 GPIOs.
140361 | Libero was crashing during the Generate FPGA Array action. | This issue was occurring because the action was trying to open a SmartDesign that was corrupted due to the use of copy / paste functionality to instantiate HDL+ cores within the SmartDesign. This issue related to the copy / paste functionality of HDL+ cores has been resolved.
140306 | There was discrepancy between the port name and pin number for the differential I/O in the Global Net report. | This issue has been resolved by indicating always using the P side of the differential I/O port in the report.
140882 | In the generated vm netlist, INIT string of MACC_PA_BC_ROM was incorrectly written in binary format, even though it is pre-fixed as 288'h in Synplify V-2023.09M (2024.1) and Synplify V-2023.09M-3(2024.2). | This INIT string of MACC_PA_BC_ROM in the generated netlist is now correctly written in hex format in SynplifyPro V-2023.09M-5.
140296 | The SSN Analyzer was experiencing crashes when used with the MPF300T-FCG784N device. | This issue has been fixed as the supported SSN Analyzer for FCG784N device used FCG784 SSO data, as both packages are identical in terms of SSO.
140136 | Synthesis failed due to an internal error, @E: BN705, during optimization stage. | This is now resolved in SynplifyPro V-2023.09M-5.
140181 | Synplify tool incorrectly reported warnings of insufficient block RAM resources even though the design didn't fully utilize block RAMs of the specific device. | This incorrect warning is now removed in SynplifyPro V-2023.09M-5.
140239 | There was an issue with reading the DSN value of RTG4 devices at the end of the programming action. | The programming algorithm has been changed to read the DSN value before exiting programming mode.
140082 | Disabling ODT for Rank0 in the PolarFire DDR3 controller IP had no effect—the I/O Editor and IBIS model continue to reflect ODT as enabled, resulting in no distinction in generated files or write behavior. | PF_ DDR3/DDR4/LPDDR3 core has been updated to remove the "ODT Activation Settings on Read" option.
140153 | There was an issue with DDR3 IBIS Model generated using Libero SoC V2024.2. | The APIs responsible for dumping the model selector for BIDIR I/Os have been corrected.
140258 | There was BA simulation errors with the 'ODT_DYNAMIC_UNIT' macro. | The 'ODT_DYNAMIC_UNIT' simulation model has been updated to enable BA simulation.
140041 | 'Generate bitstream' was failing when using an eNVM client memory file filled with 0s which exceeds 37KB size. | The software has been updated to efficiently check if the first page of eNVM is filled with zeroes.
139884 | '#N/A' was seen when MPE report was imported in Power Estimator, specifically for Transceiver related fields. | Fix has been added in Power Estimator to correctly identify XCVR lanes as well as populate certain fields with default values in places of updating with "--".
139848 | In the Aldec simulation flow, the incorrect asim command was getting generating. | The `run.do` generation has been updated to use `PolarFire asim` command for both PolarFire and PolarFireSoC devices. This resolves the previous requirement for manual `vmap` adjustment.
140190 | The output clock and data of the PF_IOD_GENERIC_TX were not centered in some cases because of an active DLL. | The issue has been fixed by adding an inactive DLL and connecting to the interface, if needed.
139519 | Compile was not checking if some pins were connected to top ports in the block mode. | The check has been added to handle such cases correctly.
139301 | Synthesis failed due to an internal error, @E: BN707, during the optimization stage. | This is now resolved in SynplifyPro V-2023.09M-5.
139341 | Libero did not error out for invalid SPI-Flash stage 3 key binding in combinations with custom security settings. | Libero now errors out for invalid combinations of SPI-Flash stage 3 key binding with respect to custom security settings.
139180 | System Controller Suspend Mode information was missing in the logs. | The System Controller suspend mode information have now been added to the logs.
139229 | SmartTime created 2 clock domains when using differential IO. | This issue has been fixed to create only one clock domain in such scenario.
139049 | Enabling the Enable RX_CLK_ODT_EN for LVDS failsafe option in the RX configurator and selecting "Clock to data relationship" as Dynamic, Centered, or Aligned (but not Fractional), resulted in a non-functional design on silicon. | The issue has been fixed and users should rerun Place and Route to see the fix.
138867 | Libero was crashing when trying to generate a SmartDesign component in a design. | This issue was occurring because the action was trying to open a SmartDesign that was corrupted due to the use of copy / paste functionality to instantiate HDL+ cores within the SmartDesign. This issue related to the copy / paste functionality of HDL+ cores has been resolved.
138956 | Complie netlist failed because of an issue with the synthesis-generated netlist. | This is now resolved in SynplifyPro V-2023.09M-5.
138852 | There were discrepancies in I/O register combining reports between the IOREG, compile and layout reports. | The compile report and layout log have been enhanced to report more details about the IOREG combining and data have been made consistent across all reports.
140526 | There was issue with PF_DDRx support for ZQCS commands. | The issues in system generated core have been fixed and validation completed for all PF_DDRx cores.
138620 | Identify Instrumentor failed with Internal Error in c_vhdl.exe for certain designs. | This issue has been resolved In Identify V-2023.09M-5.
138631 | There were issues with Globals Assigner Convergence. | Optimization objectives have now been relaxed to avoid long runtimes.
138318 | System Suspend Mode option was shown in the compile report in the RTG4 designs; users were allowed to change it later in the flow leading to confusion. | This option has been removed from the compile report since it can be changed later in the flow.
138226 | An error occurred during BA simulation on an MPF design containing a register triggered on the negative edge combined with an output. | PF_IOREG simulation model is now updated with missing timing arcs to cover different edges of clocks in BA simulation.
138474 | Generate bitstream was failing when content was filled with zeros greater than 37 KB present. | The software has been updated to efficiently check if first page of eNVM is filled with zeroes.
141664 | Multiple top-level candidates in the design were encountered which stopped the compilation. | Top module information now passes all the time in the `synplify prj` file and all conditional dependencies have been removed.
137765 | There was issue with cross-probing from SmartTime to Netlist viewer. | In Libero SoC 11.X releases, the 'Show in Chip Planner' functionality in SmartTime highlighted the selected object in the Floorplan view and created a Logical Cone in the Netlist Viewer with that object in the Chip Planner. In Libero 12.X and 202X.X releases, the cross-probing feature has been retained, but the logical cone creation part has been removed. This is because the cone already exists at the bottom of the SmartTime window. Now, the 'Show in Chip Planner' functionality in SmartTime highlights the selected item on the NLV canvas within the Chip Planner application. Additionally, it ensures that the Zoom and Center toggle is switched on for cross-probing to work as expected.
138111 | The Transceiver Configurator-generated settings for 'Lock To Data with 2x gain' for 100T were incorrect. | PF_XCVR: The CDR mode lock to data with 2x gain settings has been updated for more robust functionality.
137621 | SI values entered in configurators resulted in invalid resolutions without warning users to maintain valid ratio constraints. | The formula to compute values has been enhanced to all the supported Amplitude values (100/400/800/1200 mv).
137099 | There was huge difference in resource utilization for two identical set of HDLs. | The resource utilization of these two identical set of HDLs are now comparable in SynplifyPro V-2023.09M-5.
136902 | The constraints were not being considered in a project after unlinking and re-importing the constraint files. | Constraint file references remain part of top module even when the file that caused the issues is deleted. This issue has been resolved.
137134 | New SPI Flash Device support with FlashPro 6. | Added support for Space Grade QSPI MRAM AS302G208-0108X0MCEY.
137028 | SynplifyPro tool reports incorrect warning about `syn_radhardlevel` directive not being applied inspite of the attribute being implemented correctly | This incorrect warning is now removed in SynplifyPro V-2023.09M-5.
136789 | Synthesis fails with internal error in m_generic.exe. | This crash is now fixed in SynplifyPro V-2023.09M-5.
136573 | 'PF_IOD_TX_CCC IP' core with 3.5 clock ratio not producing the 'TX_CLK_G' output. | This issue was present for clock ratio 3.5 with data rate less than 400 Mbps as the connectivity was missing. This has been fixed.
136216 | Generated clocks were not analyzed in SmartTime UI. | This issue has been fixed in SmartTime initialization that prevented generated clock from being calculated.
138338 | IO Editor didn't allow different VICM range setting on per IO-pair basis within a bank. | The constraint on different VICM range has been relaxed in I/O Bank Assigner.
135489 | RTG4CCCECALIB Spacewire application's Clock recovery mode. | Basic tab's Exact Value for Frequency has been disabled and Actual Value has been removed. The Reference clock frequency is disabled when PLL is in bypass mode.
135423 | PF_IOD: The L0_LP_DATA and L0_LP_DATA_N of the PF_IOD_GENERIC_RX IP were toggling during the high-speed data transition. | PF_IOD_GENERIC_RX simulation model is now updated for a user to control on toggling of L0_LP_DATA and L0_LP_DATA_N during high-speed data transition through vsim commands.
135492 | New STAPL feature support is added to program Micron MT25QL01G SPI-Flash devices. | A new feature has been added to export STAPL files to program Micron MT25QL01G and MT25QL02G devices.
134870 | User control is enabled over page read and write timings. The vsim commands are utilized to emulate silicon-like timing accuracy. | The eNVM simulation model has been updated to offer user control on timings of page read and write operations.
134335 | Constraint Manager GUI did not accept negative values for simple clock uncertainty, resulting in negative edge uncertainty values being excluded from detailed timing analysis calculations. | Negative clock uncertainty has been added for jitter calculations.
141243 | The design contained modules instantiating themselves that resulted in crash and generated error: 'Unable to find the file '.edf', cannot add it to Libero project'. | This issue is now handled without a crash.
138709 | In the FDDR IP with the DQ 16-bit with SECDED enabled, the single DDR memory address location couldn't be accessed and ended up with a trap handler issue in the SoftConsole. | FDDR IP for 16-bit and 8-bit modes with ECC enabled have been updated to map top-level DQ_ECC ports correctly to FDDR_DQ_ECC[#] package pins for proper ECC functionality.
141676 | RTG4 FDDR Controller in 8-bit or 16-bit width mode with ECC enabled had a bug. | The bug has been fixed by adding a message in compile for the RTG4 FDDR Controller in 8-bit or 16-bit width mode with ECC enabled to catch the attention of users to check the documentation on how to connect the ECC pins.
131218 | Libero crashed when trying to open a project. | This issue was occurring because the action was trying to open a SmartDesign that was corrupted due to the use of copy / paste functionality to instantiate HDL+ cores within the SmartDesign. This issue related to the copy / paste functionality of HDL+ cores has been resolved.
131579 | In PF_XCVR v3.1.200, enabling the scrambler / descrambler option in 64b / 66b mode had no effect on the generated simulation model, which led to mismatched simulation behavior. | A new Gear Box option for 64B66B / 64B67B modes now adds support for expanded 64b6xb PCS configurations to independently enable scrambler / descrambler, disparity (64b/67b only), BER monitor, and 32-bit data width.
131051 | Libero was crashing when opening a project. | This issue was occurring because the action was trying to open a SmartDesign that was corrupted due to the use of copy / paste functionality to instantiate HDL+ cores within the SmartDesign. This issue related to the copy / paste functionality of HDL+ cores has been resolved.
131060 | In x16 ECC configuration, the MSS configurator incorrectly assigned ECC bits to DQ[16–19] instead of DQ[32–33], and misleadingly indicated usage of DQ[18–19] for write calibration, which is handled by the core in both x16 and x32 configurations. | MSS_DDR 16-bit with ECC enabled update ensures correct ECC byte-lane assignment in the MSS Configurator component XML and enables proper DDR memory training.
134041 | PF_IOD: There was timing check issue with the Octal PHY. | The check arcs related to pause and reset have been removed from LANECTRL simulation model to remove the unwanted warnings that appeared during BA simulation.
130222 | There was timing check issue with the Octal PHY. | Timing check related to PAUSE / RESET of LANECTRL is not applied in status timing analysis. These check arcs have been removed from timing model.
130074 | There was issue with Libero Smart Debug Eye Monitor with PolarFire XCVR design. | Intermittent eye collapse issues have been resolved during lane tests and traffic. Intermittent 0- Eye opening is now observed if there is signal integrity setting mismatch between Tx and Rx.
92700 | PF_DDR3/4: Warnings were observed in Fast training mode simulations. | PF_DDR3 / DDR4 / LPDDR3 cores are now updated to remove simulation warnings related to Read Gate Training & Fast simulation warnings.
127207 | Libero crashed when trying to open a project. | This issue was occurring because the action was trying to open a SmartDesign that was corrupted due to the use of copy / paste functionality to instantiate HDL+ cores within the SmartDesign. This issue related to the copy / paste functionality of HDL+ cores has been resolved.
128190 | Incorrect error message was printed when 'download_latest_core' command was called with no internet access. | A functionality has been added to check the internet access. If there is no access, the user is notified.
126645 | Libero crashed when trying to open a project. | This issue was occurring because the action was trying to open a SmartDesign that was corrupted due to the use of copy / paste functionality to instantiate HDL+ cores within the SmartDesign. This issue related to the copy / paste functionality of HDL+ cores has been resolved.
124376 | Libero does not checkout the license from the 2nd floating server specified in 'LM_LICENSE_FILE' when all seats of the first floating server are occupied. | See section Availability of Multiple Servers in LM_LICENSE_FILE Environment Variable.
120591 | New feature support to show MSS DDR memory training results. | A new feature is introduced to display MSS DDR memory training results.
123950 | The `get_clocks` command has been resolved to registers in exception constraints, resulting in the command ignoring input and output delays. | `get_clocks` command for the -from and -to options for all exception constraints (`set_false_path`, `set_max_delay`, `set_min_delay`, `set_multicycle_path`) have been resolved on clock objects instead of all clock pins(or data pins for -to options) of the registers from that clock domain. Resolving `get_clocks` on clock objects solves the exceptions matching on input to register and register to output paths.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2025.1 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 2-3.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary | Resolution
--- | ---
CoreAXI4SRAM is an invisible core in the catalog. | CoreAXI4SRAM is now hidden in the catalog.
Libero web links have been updated from 'Microsemi' to 'Microchip'. | The start page has been updated with new links and the connection checking logic has been changed to support new links.
PF_LSRAM simulation model is enhanced to support ECC error injection. | Verilog task & Python script-based solution has been introduced to emulate/simulate the ECC flag assertion. Users can now use this solution with any existing Libero project but only with 2025.1 simulation libraries. The changes in user design afre only limited to `run.do`.
Invalid temperature ranges are now accepted using TCL to generate a new project. | A new check has been added in the TCL command to restrict users from setting a custom range for the PolarFire and PolarFireSoC families. The same check has already been added for UI for hiding the custom range in 'Project' settings.
Programmer Detection should be automatic for new projects and TCL script. | The parameter `-programmer`for command `auto_construct_job_project` is now optional. If the parameter is omitted and a single programmer is connected to the host machine, the command executes successfully.
Libero SmartDebug SI settings persistence shows modified settings in subsequent SmartDebug launches which may not match actual settings in the device. | The SmartDebug SI settings feature now includes a pop-up message prompting users to choose between user-configured settings and modified settings when loading parameters. Additionally, a radio button on the SI settings UI allows users to switch between these two options.
Projects targeting PolarFire family FPGA and SoC device part numbers offered in MIL or automotive T2 temperature grade now supports IND range for Analysis Operating Conditions used by static timing and power analysis. | Project Settings option is now used to select the IND range for Analysis Operating Conditions used by static timing and power analysis. This enhancement allows designers using MIL or T2 devices in systems that do not operate beyond the IND range to analyze static timing and power at more applicable conditions.
Lane controller timing model doesn't match user configuration options. | Lane controller timing model is updated by adding delay step into arc delay calculation.
Enabled Repair Hold Violations of Source-sync Interface during P&R with Repair Minimum Delay Violations. | See section PF_IOD_GENERIC_TX Hold Violations Repair.
P&R interpretation of single asynchronous clock group timing constraint. | Clocks belonging to a single asynchronous clock group timing constraint won't be asynchnronous to each other.
Timing of some path constraints on output ports were missing in placer. | Timing propagation has been enabled to handle max / min-delay constraints on output ports. Also, the bus index has been added in importer to locate relevant port names.
Timing analysis ignored generated clock with register clock pins as source. | Generated clock now correctly analyzes in this scenario.
Clock generation was 0 when the source is a bidirectional port. | This issue has been fixed when a generated clock is set on a bidirectional I/O that prevented the clock generation to be calculated correctly in min-delay analysis.
Identify tool to support pre-armed triggers for RTG4 devices. | Identify V-2023.09M-5 now supports pre-configuring or pre-arming triggers that allows capturing error events that occur immediately after reset during startup or initialization before the system is operational.
RAM inference was incorrect and registers were getting inferred in addition to LSRAMs. | Register packing now happens correctly and only LSRAMs are inferred in SynplifyPro V-2023.09M-5.
Simulator and port width mismatches simulation warnings. | PF_DDR3/DDR4/LPDDR3 cores are now updated to remove simulation warnings related to Read Gate Training & Fast simulation warnings.
New part numbers added. | The new part numbers, MPFS025TS-FCSG325T2, PolarFireSoC, MPFS025TS, FCSG325, STD, and TGrade2, have been added to the software.
There were issues in meeting min-delay timing without RTL changes. | The search scope has been expanded for inserting delay buffers in min-delay repair.
In the absence of 'sdf' file, the P & N path tool different delay values until they were compared at IODPAP_IN_VCCI macro & hence, comparison was showing some unknows. | The IOPADN_IN_VCCI simulation model is updated by correcting the default delay of 10 ps
License checks have been added post creation for partner IPs. | Libero SoC now have licensing checks for partner IPs at the time of creation as well as after creation.

Rev: 2025.2

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