Jump to main content

# 5.2 Changes That Address Important Issues

(Ask a Question)

## 5.2.1 PolarFire FPGA, PolarFire SoC, and RT PolarFire FPGA

(Ask a Question)

### 5.2.1.1 RC Oscillator-Derived Constraint for Frequency Accuracy

(Ask a Question)

The frequency accuracy specifications for the internal RC oscillators in PolarFire, PolarFire SoC, and RT PolarFire devices have been updated to account for device aging effects. Refer to the latest device datasheets for the updated specification. To support this change, the Libero SoC derived timing constraints for the internal RC oscillator has been enhanced to account for the updated frequency accuracy specification based on the project operating conditions range selected. You need to review the timing constraints and timing exceptions when you update Derive constraints on an upgraded design containing the internal RC Oscillator.

## 5.2.2 RTG4

(Ask a Question)

### 5.2.2.1 Functionality of Instantiated CLKINT Tied to Logic '1'

(Ask a Question)

The RTG4 Place and Route process has been enhanced to support the rare corner case, where a CLKINT global promotion buffer has been instantiated and tied to a static logic '1'. Although using a global resource to carry a static '1' is not expected in a real-world design, Libero SoC v2024.1 resolves a corner case issue, where a half-chip (left or right) Global Buffer (GBL or GBR) that is tied to static '1' can instead follow the logic value of a user fabric signal promoted to the corresponding other half-GB. Prior to Libero SoC v2024.1, in the unlikely event that a CLKINT has been instantiated and tied to a static '1', the user would either remove such a scenario from the design or manually instantiate a BUFD buffer with its input tied to '1' and its output connected to the CLKINT.

### 5.2.2.2 RC Oscillator-Derived Constraint for Frequency Accuracy

(Ask a Question)

As part of continuous enhancements to RTG4 design flows, Libero SoC v2024.1 enhances the automatically derived timing constraints for the internal RC oscillator. It accounts for the existing frequency accuracy specification in the RTG4 device datasheet.

Prior to Libero SoC v2024.1, users would have to manually account for the worst-case frequency accuracy specification in the RTG4 datasheet during Static Timing Analysis (STA). If upgrading an existing design to Libero v2024.1 and re-deriving the timing constraints, make sure the manually entered constraints do not conflict with the enhanced automatic RC Oscillator timing constraints, before re-running STA. For more information, see the RTG4 Clocking Resources User Guide.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.