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# 4.6 Migrating Designs to Libero SoC

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## 4.6.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2024.1. For more information about updating a core version, see section Updating a Core Version.

Table 4-5.Core Enhancements and Upgrades
Core | 2024.1 Version | Status | Comments
--- | --- | --- | ---
PF_IOD_CDR | 2.4.110 | Production | See section PF_IOD_CDR: EYE_MONITOR_WIDTH Parameter Selection.
PF_SYSTEM_SERVICES | 3.0.103 | Production | See section New RTPF500ZT/TS/TL/TLS Devices.
RTG4FDDRC, RTG4FDDRC_INIT | 2.0.104 | Production | Added fractional clock frequency support for the Tcl parameter PLL_CLK_FDDR_FREQ. The RTG4FDDRC core can now be configured and generated successfully in GUI configuration, or with a Tcl script executed in GUI or in batch mode, with the parameter PLL_CLK_FDDR_FREQ configured with a fractional frequency.

## 4.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right-click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

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