Jump to main content

# 8.7 Resolved Issues

(Ask a Question)

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2022.2 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 8-10.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Summary | Resolution
--- | --- | ---
00910093 | MPF Programming issue with Zeroize and Authentication `PROC_ENABLE`. | `ENC_DATA_AUTHENTICATION`, `ZEROIZE_LIKE_NEW`, and `ZEROIZE_UNRECOVERABLE` actions now pass for exported bitstream file/FlashPro Express job when include plaintext passkey is checked and these actions are disabled in the Configure Security tool.
122358 | If the PolarFire CCC is configured in Post-Divider Feedback Mode, the phase shift continuously changes after power cycling the device (Core Version 2.2.100). | For information, see section PLL Phase Alignment when Using Post-Divider or External Feedback Mode.
00998202 | The `vdir` command used with ModelSim ME Pro 2021.3 for pre-compiled libraries delivers the incorrect result of unknown version. | This issue is resolved with the ModelSim ME Pro provided with Libero v2022.2.
493642-2872943656, 493642-2880122269, 00850681 | RTG4_CCC: Simulation of RTG4 Design using a FCCC PLL with external feedback: phase delay is not adjusted. | For information, see section Added Simulation Support for RTG4 PLL Feedback Delay.
00967580 | RTG4_ODT: Dynamic ODT macro simulation library bug. | The `ODT_DYNAMIC` simulation model has been updated to match the port names with libero generated files.
— | A deadlock condition with the RTG4FCCCECALIB core occurred when configured for external feedback mode and output option-1 to hold the outputs LOW until the lock asserts. | If External Feedback is selected and the FB_CLK source is one of the CCC's GLx outputs, your CCC output setting of Hold outputs LOW until PLL locks is ignored for the GLx that is sourcing the `FB_CLK` and that GLx is allowed to operate prior to lock assertion.
— | When setting permanently write protect fabric in Configure Permanent Locks tool, the exported bitstream file/job will also program sNVM update protection to be locked for update (i.e., protected by Flashlock/UPK1) even though sNVM updates were allowed without Flashlock/UPK1 in Configure Security tool. | Security settings for Fabric and sNVM can now be saved or read separately.
— | Installing Libero SoC v2022.1 on a Personal Computer (PC) running windows causes the PC to restart unexpectedly without providing a notification message. | To avoid this issue, install Visual C++ Redistributable 2015-2022 x86 on the PC before installing Libero SoC v2022.1.
01037234 | Stage3 Initialization Client data of the Golden and Update images is not available in the exported SPI Flash image. | The Export SPI Flash Image tool now exports data for STAGE3 initialization client imported via SPI Bitstream client in the SPI-Flash tab of the Configure Design Initialization Data and Memory tool.
912639 | HDL_LANGUAGE: VHDL: Libero is not parsing files correctly to pass to Synthesis. | Libero is not parsing the dependent package files correctly to pass to Synthesis.
967427 | G4: Sanitize option is increasing stpl file size unexpectedly. | Generate Bitstream, Export Bitstream, and Export FlashPro Express Job tools do not unnecessarily include entire fabric data when sanitizing eNVM as part of an ERASE action.
493642-2092580450, 493642-2707760243 | Add information for `update_and_run_tool` in the Libero online help. | A tool state can be Out of Date (OOD) for various reasons, such as when there is a change in the source files, a change in settings, a parent tool state cleaned, or out-of-date. If a tool is out of date, the `update_and_run_tool` Tcl command considers the updated source files and settings and runs all of its parent tools if they are cleaned or out of date, and then runs the specified tool itself.
493642-2868126969 | COMPONENT_MANIFEST: Include SDC in manifest text files of SmartDesign generated Core IPs. | For information, see section Constraint Files in the Manifest Text Files of Generated Core IPs.
964688 | Update the Libero SoC Linux Environment Setup User Guide . | The wizard for installing Libero SoC v2022.2 has been streamlined and simplified while allowing you to control what gets installed.
00938240, 00972272 | If reserve pins for probes is unselected, System Controller suspend mode is unavailable. | When configuring programming options, the Disable probe read/write option depends on a Constraints Manager option that reserves pins for the probe. If the reserve pins for probe option are not selected, probe read/write must be disabled and cannot be changed. Default for the disable probe read/write is based on the current reserve pins for probe setting: off and available for you to change if pins reserved or on and unchangeable if pins are not reserved.
939458 | Add a popup when discrete clock is selected in the Programmer Settings dialog. | In addition to adding a pop-up warning in the Programmer Settings dialog, a warning is added when you perform a Program, Verify, Erase, or Authenticate action to advise you about significant programming time increase in case the discrete clock mode is set for the selected programmer
910093 | FlashPro 6 turbo (SPI-Slave): MPF Programming issue with Zeroize and Authentication PROC_ENABLE. | Added zeroization support for secured devices.
906419 | KIT_LICENSE_IP: Gold License has an issue with Mi-V running on MPF300T. | Close and reopen the Libero project.
959171 | KIT_LICENSE_IP: The CoreUARTapb v5.7.100 FIFO depth has an issue with the gold license. | Close and reopen the Libero project.
493642-2784815561 | PF_PCIE: PF_CRYPTO: DRC check for PCIe and Crypto configurator when the clock frequencies are between 70 to 125 MHz. | Confirmed that in PolarFire SoC designs, DRC checks for PCIe and Crypto configurator when clock frequencies are between 70 and 125 MHz.
493642-2695344599 | RTG4_CCC:CCC Core Generation is failing for some Lock Window values. | The RTG4FCCC and RTG4FCCECALIB cores are updated to show DRC for unsupported ppm values.
886516 | Place and Route Globals Assigner failure with MPFS250T-FCSG536E device. | Select the appropriate pin type that can drive GBs or PLLs as needed, and then use the INBUF+CLKINT solution and have IO Bank Assigner infer a hardwired connection if available.
860917 | PF_IOD_GENERIC_RX Fabric Global Clock from external Source. | Updated `RX_CLK_G` and `RX_CLK_TO_PLL` ports visibility in symbol view.
941837 | RTG4FCCC/RTG4FCCCECALIB: Expose GLx_Yx_ARST_N in CCC configurator GUI. | For information, see section Changing Default Behavior of GLx_Yx_ARST_N Signals in the CCC Configurator.
968882 | Repair min delay affects max timing closure. | Automatically generated clock jitter does not impact min-delay timing.
878534 | STPS-373 - SmartTime in v2021.2 considers invalid false path constraint. | Applied false path constraints now work properly and warnings about invalid false path constraints no longer appear.
904319 | STPS-381 - Constraint Editor GUI column width issue in Libero v2021.2 and v2021.3. | The constraint browser pane on the left side can now be reduced and increased without issues or standard column width.
1001850 | Clock generation value is 0 ns for muxed clocks in Libero v2022.1. | Fix SmartFusion2/IGLOO2 zero clock generation delay for muxed clocks.
868286 | PF_SOC: MSS: Warning if MSS_QSPI and SPI I/O config is split between MSSIO and Fabric. | The PolarFire SoC MSS Configurator is updated to print a warning message if the QSPI/SPI peripherals are split between MSSI/Os and Fabric I/Os.
980695 | PolarFire Post Compile does not route the N pins of the differential Buffer. | The `OUTBUF_DIFF_IOG` and `TRIBUFF_DIFF_IOG` macros have been updated to include the connection from the IO to IOPADN for the E and D pins.
998202 | ModelSim ME Pro 2021.3 PC version only `- vdir` command is giving results as unknown version. | This issue is resolved with the ModelSim ME Pro provided with Libero v2022.2.
00907718, 00987912 | Create_generated_clock issues warning. | This issue is resolved with the ModelSim ME Pro provided with Libero v2022.2.
493642-2820955992 | IBIS model of the I2C Component of Airbus issue. | For BIDIR pins, both Input and Output IBIS models are exported.
950237 | The IBIS modes for the LVDS inputs for RTMPF are not getting generated. | LVDS Input side IBIS models are generated as expected for RTPF device.
971142 | SmartTime and PnR Jitter report has 25 ns as jitter for the `PLL_OUT3` clock. | Changed the jitter value for PLL output to cap at 16.667 ns when the frequency is lower than 1.5 MHz.
996553 | M2S MDDR and FDDR register initialization compared to the RTG4 FDDR initialization. | The IGLOO2 FDDR Core ABC Register initialization is now similar to RTG4 FDDR.
493642-2771429137 | SmartFusion2 eNVM1 remap defeature. | For information, see section Prevent Remapping Data from eNVM_1 Memory Block to Cortex-M3 Code Space.
959860 | PF_XCVR: XCVR configurator incorrectly setting register bit. | Add the `PMA_CTRL_RO` register value after all the registers are processed at the end of the assembly file, and then use the MODE2 option to generate the mem file and bitstream.
— | For PolarFire SoC Libero designs that contain eNVM, running VERIFY_DIGEST after programming device fails with the message eNVM digest verification: FAIL. | The eNVM client in Configure Design Initialization Data and Memories tool has a new option to include pages for digest calculation, which resolves this issue. See section eNVM Client Digest Option.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2022.2 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 8-11.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary | Resolution
--- | ---
Timing analysis reports same path twice. | Verified that all paths are reported for the clock domain and that the clock domain for CCC output is not created.
PF TAMPER macro outputs need latching when using System Controller Suspend mode | For information, see section PF_TAMPER Enhancement to Latch Outputs when Using System Controller Suspend Mode.
Add support in TCL for location coordinates for each element instantiated in canvas. | Added the new option in the Export Component Description (TCL) dialog to also export SmartDesign presentation model. Exported presentation model (`*.pm`) files can be used to recreate SmartDesign presentation by the newly added `sd_apply_presentation` TCL command.
New Flash device support: IS25LP128 from ISSI vendor. | Add programming device support of IS25LP128 with FlashPro 6.
Developer mode GUI option is not intuitive. | The Create New Job Project dialog has more information about how to create a new project in case you do not have a job file and how to switch to developer mode. The current mode, operator, or developer is always shown in the FlashPro Express title.
PF_CCC: PLL_LOCK configuration missing. | For information, see section PLL Phase Alignment when Using Post-Divider or External Feedback Mode.
PF_CCC: Backup clock is not supported in External and Post-Divider Feedback Mode. | For information, see section PLL Phase Alignment when Using Post-Divider or External Feedback Mode.
PF_CCC: Reset on lock in Post-VCO Mode. | For information, see section PLL Phase Alignment when Using Post-Divider or External Feedback Mode.
SmartPower crashes while exporting MPE report. | Added condition to handle null values while exporting MPE report.
SSN Analyzer: DEF0012: Unable to open file SSNAnalyzer.def: line 56: 20245 Segmentation fault. | Exported the file to the staging area.
Add `THIS FILE IS AUTO GENERATED DO NOT MODIFY` statement in derived constraint file. | A message now appears if modifications to a derive constraints file will be lost.
Incorrect violations reported in constraint coverage. | Setup violations in coverage reports are zero when report violations have zero violations.
PF_SOC: MSS: Point out to users that scratchpad memory for HSS/Linux systems. | To ensure that sufficient scratchpad memory is allocated to the bootloader using the L2 Cache tab, a warning message now appears if `SCRATCHSIZE` is less than 4 (512 KB) in GUI and batch mode.
PF_SOC: MSS: MSS missing the port BOOT_FAIL. | Added an Expose Boot Status ports check box that, when checked, exposes the `BOOT_FAIL_CLEAR_F2M` and `BOOT_FAIL_ERROR_M2F` ports to users.
PF_SOC: MSS: MSS_I2C - Fabric Interface missing inverter for open drain I/O. | If fabric is selected for I2C for production device, inverters have been added for the following ports: `I2C_0_SCL_OE_M2F` `I2C_0_SDA_OE_M2F` `I2C_1_SCL_OE_M2F` `I2C_1_SDA_OE_M2F`
RTG4 CCC/PLL: Clock Uncertainty: RTG4 CCC/PLL must also derive clock jitter constraints per DS jitter specification. | For information, see section New Timing Constraint Flow Accounts for Global Clock Jitter Automatically .
Libero does not generate IBIS models for PolarFire EXT temp grade. | EXT temperature range supported for IBIS.
Export Job Manager data step does not include information about back-level bypass. | Added an option for bypassing back-level protection for Recovery/Golden bitstreams. The selected setting is saved in the JDC file and passed to the Job Manager.

Rev: 2025.2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.