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# 7.6 Migrating Designs to Libero SoC

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## 7.6.1 Core Enhancements and Upgrades

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The following table lists core enhancements and upgrades in Libero SoC v2022.3. For more information about updating a core version, see section Updating a Core Version.

Table 7-4.Core Enhancements and Upgrades
Core | 2022.3 Version | Status | Comments
--- | --- | --- | ---
PF_IOD_TX_CCC | 1.0.128 | Production | Allows a non-integer data rate.
PF_TAMPER | 1.0.212 | Production | See section Designs Containing TAMPER Core's PORDIGEST.
PF_SPACEWIRE_RX_PHY | 1.0.109 | Production | The Data Rate field supports integer values between 0-400 Mbps as well as non-integer data rates.
PF_SRAM_AHBL_AXI | 1.2.110 | Production | `PF_SRAM_AHL_AXI` configured with the AXI interface and read-interface no longer fails to generate from a TCL script.
PF_RGMII_TO_GMII | 1.3.107 | Production | Repackaged with the latest `PF_CCC`, `PF_IOD_GENERIC_RX`, and `PF_IOD_GENERIC_TX` core versions.
PF_QDR | 1.9.102 | Production | Repackaged with the latest `PF_CCC` core version.
PF_IOD_OCTAL_DDR | 2.0.106 | Production | Repackaged with the latest `PF_CCC` core version.
PF_PCIE | 2.0.118 | Production | See section New INTx Interrupt Selection.
PFSOC_TAMPER | 2.0.100 | Production | See sections Designs Containing TAMPER Core's PORDIGEST and New PFSOC_TAMPER Core Including eNVM POR Digest Check.
PF_IOD_CDR_CCC | 2.1.111 | Production | Applies derived constraints when the core instance is TMRed.
PF_IOD_GENERIC_RX | 2.1.110 | Production | Repackaged with the latest `PF_CCC` core version.
PF_CCC | 2.2.220 | Production | See sections Designs Using PF_CCC IP Core and TMR of Registers in External Feedback and Post-divider Modes.
PF_LPDDR3 | 2.3.118 | Production | Repackaged with the latest `PF_CCC` core version.
PF_DDR3 | 2.4.120 | Production | Repackaged with the latest `PF_CCC` core version.
PF_IOD_CDR | 2.4.105 | Production | Applies derived constraints when the core instance is TMRed.
PF_DDR4 | 2.5.109 | Production | Repackaged with the latest `PF_CCC` core version.

## 7.6.2 Updating a Core Version

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Perform the following procedure to update a core version:

1. Download the latest version of the core into your vault.
2. Upgrade each configured core in your design to the latest version by right-clicking the core component in the design hierarchy and selecting Update Component Version. The component is regenerated automatically.
   Important: The Update Component Version option is now available on instances of core components in a SmartDesign canvas as well. In addition, the selected core version is downloaded automatically from the Update Component Version dialog itself if needed.
3. Review the SmartDesign components and user RTL files in which the core component has been instantiated. If the port-list of the core component is modified after updating to the new core version, right-click the core component's instance in the SmartDesign and select Update Instance to update its port-list. Check for any pin/port disconnections in the SmartDesign or for any new pins exposed on the core component's instance, and then connect them or tie them off as needed and regenerate the SmartDesign component.
4. Build Design Hierarchy and Derive the Timing Constraints again from the Constraint Manager tool to use the latest generated core timing constraints.
5. Rerun the design flow.

Rev: 2025.2

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