Jump to main content

# 11.2 Changes that Address Important Issues

(Ask a Question)

Libero SoC v2021.3 includes changes that address certain important issues.

## 11.2.1 PolarFire/PolarFire SoC – Change to Default Settings of Specific Unused I/O Pins

(Ask a Question)

Prior to Libero SoC v2021.3, programmed I/O defaults in PolarFire/PolarFire SoC designs for a specific subset of unused I/O pins would glitch at power up. (In this context, the fabric is programmed, but the I/Os are unused in the design.) If impacted I/O pins are connected on system, the PCB designer should be aware that they can glitch using Libero SoC-generated defaults. Such designs will get updated to the corrected new default setting if the Generate FPGA Array data tool is rerun in Libero SoC v2021.3 or later.

Note: This change was made to Libero SoC programming only. There have been no changes to the PolarFire or PolarFire SoC products.

## 11.2.2 RTG4 – MSIO/MSIOD Input IOPAD Timing Update

(Ask a Question)

When the Libero SoC project-level `SET` mitigation setting is disabled, RTG4 MSIO and MSIOD input buffer delays have been updated to reflect the silicon behavior which, in the case of MSIO and MSIOD, are always mitigated regardless of the `SET` mitigation setting.

The impact of this timing update on the internal regression suite of designs does not show any occurrence of new violations. The maximum performance degradation is well below our built-in timing model margin compared to the actual silicon performance.

## 11.2.3 PolarFire, PolarFire SoC, RT PolarFire – Octal PHY Differential DQS Output

(Ask a Question)

The `PF_IOD_OCTAL_DDR` core has been enhanced in Libero SoC v2021.3 to support differential DQS I/Os. To use this feature, check the Enable Differential DQS option.

Note: Currently, this is a beta feature while it is being validated.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.