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# 3.4 Software Features and Enhancements

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## 3.4.1 Ignore Clock Latency Constraint on CDC Data Paths

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Libero SoC v2024.2 supports static timing analysis to ignore_clock_latency when using set_max_delay and set_min_delay constraints. This support is useful for analyzing the data path delay on paths such as clock domain crossings (CDCs) while excluding clock path delay, clock skew, and clock jitter.

## 3.4.2 Improvements in Quality of Results and Place and Route Runtime

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As part of our commitment to continuous improvement for Libero SoC Design Suite, the v2024.2 release improves Place and Route runtime and Quality of Results.

- A 10-13% average runtime improvement has been achieved across designs that use SmartFusion2, IGLOO2, RTG4, PolarFire FPGA, and PolarFire SoC family devices.
- Using RT PolarFire with synthesized Triple Module Redundancy flow improved QoR by roughly 17% over previous releases, with a 17% reduction in runtime.

## 3.4.3 Synplify Pro ME Attribute for FSM Error Correction Using Hamming Distance-3 Encoding

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For Libero SoC v2024.2 and later versions, Synplify Pro ME supports using the syn_fsm_correction attribute to implement FSM single-bit error correction (SEC) logic using Hamming distance-3 encoding. To achieve the implementation of single-bit error correction (SEC) logic using Hamming distance-3 encoding, apply the attribute `/* syn_fsm_correction="hamming3" */` directly on the RTL module.

## 3.4.4 Synplify Pro ME and Identify ME Tools Upgrade

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Libero SoC v2024.2 supports V-2023.09M-3 versions of Synplify Pro ME and Identify ME tools.

The following are key enhancements in Synplify Pro V-2023.09M-3:

- If a virtual clock with an input delay exists between an external port and an internal signal, the path is recognized as a safe CDC path. CDC reporting is similar to the case when there are two base clocks in the design and a constraint like a false path or asynchronous clock group constraint is applied between the base clock and virtual clock. The number of synchronizer flip-flops will be analyzed to detect whether the CDC path is safe.
- Performance is enhanced for Wide Multiplier implementation.

## 3.4.5 ModelSim ME Pro and QuestaSim Pro ME Simulator Tools Upgrade

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Libero SoC v2024.2 supports the upgraded v2024.2 versions of ModelSim ME Pro and QuestaSim Pro ME simulation tools. This will be the final Libero SoC release with ModelSim ME Pro as the default simulator.

## 3.4.6 Operating System Upgrade and Support

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Libero SoC v2024.2 introduces support for the RHEL/Alma (8.3-8.10), SUSE 12 SP5, and Ubuntu 20.04.6 operating systems.

## 3.4.7 FlexLM Upgrade

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Libero SoC v2024.2 upgraded FlexLM licensing to v11.19. Siemens’ daemon for ModelSim ME Pro and QuestaSim Pro ME licenses changed from “mgcld” to “saltd”.

Before launching Libero, upgrade all existing licensing daemons on the license server by downloading and setting up the latest daemon package from the Daemons Downloads link on the following Microchip web page: https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions.

Rev: 2025.2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.