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# 8.5 New Silicon Features and Enhancements

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## 8.5.1 PolarFire, RT PolarFire, and PolarFire SoC

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### 8.5.1.1 PF_TAMPER Enhancement to Latch Outputs when Using System Controller Suspend Mode

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The `PF_TAMPER IP` core has been updated to latch the `FLAGS[13]` and `RESET_REASON[4:0]` outputs. This is required to maintain the IP outputs when using system controller suspend mode. To enable this feature, check the option Latch System Controller Outputs in the IP configuration dialog and connect the generated core’s `CLK_FROM_RCOSC_160MHZ` input port to the internal 160 MHz RCOSC.

### 8.5.1.2 RT PolarFire SpaceWire RX PHY Core

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RT PolarFire FPGAs have been validated to support SpaceWire operation at up to 300 Mbit/sec (STD speed grade) and 400 Mbit/sec (-1 speed grade) using a third-party SpaceWire controller IP core connected to the Libero SoC v2022.2 IP Catalog SpaceWire RX PHY core.

For more information, including recommended SpaceWire RX PHY IP core configurations and pin assignments when implementing SpaceWire receiver interfaces on RT PolarFire FPGAs, see the RT PolarFire FPGA User I/O Guide.

### 8.5.1.3 Enhanced SmartBERT Core for 10 Gbps Protocols

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SmartBERT core (CoreSmartBERT) version 2.9 has been enhanced to support 10.3125 Gbps data rates.

For more information, see CoreSmartBERT Release Notes and CoreSmartBERT User Guide.

### 8.5.1.4 Additional Checks when Creating SPI Bitstream Clients

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Libero SoC v2022.2 performs additional checks (for example, matching a SPI Bitstream file target device with a Libero SoC target device) during SPI Bitstream client creation in the Configure Design Initialization Data and Memory tool when importing a SPI bitstream file generated from Libero SoC v2022.2.

Important: These additional checks are not performed when importing SPI bitstream files from pre-existing Libero v2022.1 and older releases.

## 8.5.2 PolarFire SoC

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### 8.5.2.1 eNVM Client Digest Option

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Libero SoC v2022.2 adds an option to include eNVM client pages in digest check calculations as part of VERIFY_DIGEST action. For more information, see the eNVM Tab topic in the Libero SoC Design Flow User Guide and the Libero help documentation.

### 8.5.2.2 Support Added for Secure Production Programming Solution (SPPS) Flows

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The SPPS flow has been extended and is now available on PolarFire SoC devices. This includes adding support for Job Manager and HSM-based bitstream generation flows on PolarFire SoC devices.

For more information, see the Secure Production Programming Solution (SPPS) and Job Manager User Guide .

### 8.5.2.3 PFSOC_INIT_MONITOR Core

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The PFSOC_INIT_MONITOR core version 1.0.304 has been upgraded from Pre-production to Production.

For more information, see section Core Enhancements and Upgrades

### 8.5.2.4 New Speed Mode Selection in MSS Configurator

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The MSS configurator user interface has been enhanced to include a Speed Mode selection for the following peripherals:

- I2C
- SPI
- SD/SDIO
- EMMC

For more information, see the Standalone MSS Configurator User Guide for PolarFire SoC .

### 8.5.2.5 Support Added for Locking MSS Registers and Design Initialization Data Report

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To prevent a configured MSS register values from being changed, the `<libero project>/designer/<root>/<root>_init_config_lock_bits.txt` file has been updated to support locking MSS registers.

Registers are unlocked by default and you can edit the generated file to lock the registers by specifying a value of 0. To apply the changes, use the Configure Register Lock Bits tool to source the modified file.

### 8.5.2.6 PolarFire SoC MSS DDR Initialization with Memory File in Simulation

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The PolarFire SoC MSS simulation model has been enhanced to support initialization of DDR memory. The DDR memory can be initialized with `.mem` file, which helps in many applications by allowing you to perform first AXI write transactions.

For more information, see the MSS Simulation User Guide for PolarFire SoC .

### 8.5.2.7 SPI Flash Programming Enhancements

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Added support for the new SPI-Flash device IS25LP128 from ISSI vendor.

Rev: 2025.2

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