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# 7.5 New Silicon Features and Enhancements

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## 7.5.1 PolarFire, RT PolarFire, and PolarFire SoC

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### 7.5.1.1 TX_PLL: Enable Tx Lane Alignment

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The Transmit PLL clock generates a reset signal along with the transmit clock. After the reset is asserted/de-asserted, Tx clocks usually are halted until the SERDES channels exhibit a very low skew. Libero SoC now provides the option to reset multiple serializer channels that receive the Transmit clock from one PLL at the same time. For more information, see the PolarFire Family Transceiver User Guide .

### 7.5.1.2 Export Bitstream: Custom Security

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Enhanced software to automatically include plaintext passkeys in UEK1/2 bitstream files when required for updates.

## 7.5.2 RTG4, SmartFusion2, and IGLOO2

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### 7.5.2.1 Post-Layout Editing of I/O Signal Integrity and Delay Parameters

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Libero SoC v2023.1 introduces a new tool in the Design Flow that allows users to tune I/O attributes and external timing without having to rerun Place and Route. Input is provided using a PDC file. From the Design Flow menu, double-click Edit Post Layout Design to open a file selection dialog box for selecting the input file.

In batch flow, you can issue the command `edit_post_layout_design <input.pdc>`.

The PDC file contains one or more invocations of two PDC commands:

- `edit_io`
- `edit_instance_delay`

For more information about these commands, see the PDC Commands User Guide for SmartFusion2, IGLOO2, and RTG4 .

To assist you in ascertaining which instances can have delays updated by this tool, the Place and Route tool generates a new report file named `<root>_delayinstance.rpt`. This report has an Editable? column, with Yes and No values that indicate whether a delay parameter can be edited by this tool.

The PDC commands fail if the syntax is incorrect, the referenced instances do not exist, or the values are out of legal ranges. If the batch command fails, the layout state of the design does not change. If the batch command succeeds, the layout state changes to reflect the values in the PDC commands, pin report and delay instance report files are regenerated to reflect the latest values, and the downstream tools Verify Timing, Verify Power, Generate FPGA Array Data, and Generate Back Annotated Files are invalidated.

For more information, see the Libero SoC Design Flow User Guide .

Rev: 2026.1

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