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# 7.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2022.3 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 7-5.Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number | Summary | Resolution
--- | --- | ---
493642-2836560991 493642-2874552420 00956326 01004315 | RT PolarFire, MPF500T: Design contains encrypted blocks and Synthesis (or Compile) fails with the following message: `Error: NETLIST:011 Module or UDP : (some_module) is not defined. FILE <null> LINE 0` | From the Libero SoC v2022.3 release, compile no longer generates an error when: Larger devices are used. There are two instances in the VM file with two encrypted modules, and one uses the other one‘s synthesis.
01064925 01075064 | PolarFire, RT PolarFire and PolarFire SoC: The following SPI bitstreams for devices cannot be used as SPI bitstream clients in Libero 2022.2 using a Silver and Gold licenses. Silver license: affected devices: MPF300TS MPF300TS_ES MPF300T MPFS250T_ES MPFS250T Gold license: affected devices: MPF300TS MPF300TS_ES MPF300T | This issue has been fixed.
01057217 | Using SmartDebug > Transceiver View > Register Access generates the following error message if you try to access register lane on Quad 4 and Quad 5 for the MPF500 devices: `Error: Added Register List is empty.` | Quad 4 and Quad 5 lane access has been enabled for SmartDebug while using MPF500T device.
906939 | SmartFusion2/IGLOO2 RAM1K18 primitive with WMODE=1 always uses "feed-through" access time, instead of read access time. | See section LSRAM Feed-through Write Delay.
00914404 | All families: Warn when the programming cycle count exceeds recommended limit. | Printing info and warning messages are generated when the programming cycle count is close to the max value.
01004578 01029111 | Get Training Data Failure: RTPF500T | RTPF500T DDR Training Data has been updated for different DDR corner placement such as `NORTH_NW` and `WEST_SW`.
1004578 | SmartDebug issue with 64-bit DQ width. | Smart Debug supports the 72- bit DQ width for DDR3.
1018965 | DDR4 debug issue with an instance nets name change. | SmartDebug does not prune instance names that are modified in Netlist Viewer for designs that contain a DDR4 plus a native interface.
1056838 | PolarFire PCIe core does not support INTx. | See section New INTx Interrupt Selection.
908043 | Identify Instrumentor crash in Libero SoC v2021.3. | Identify Debugger S-2021.09M-SP2 bundled with Libero 2022.3 fixes a crash that dumps Error in job: `identify_db_generator`.
493642-2699414738 493642-2850555370 | Compile crashes when FHB is enabled. | See section SmartDebug FPGA Hardware Breakpoint Enhancements.
899419 | Gate-level simulation issue with RTG4 FDDR DDR3. | See section Back-annotated Simulation of Differential I/O Connected to the FDDR Controller Hard-IP Block.
493642-2778637265 | SPI clock frequency in third stage client. | The 1(80 MHz) option has been removed from the GUI and Tcl flow of the Design Initialization Data and Memories tool.
857755 | Syntax errors with VHDL for arrays in Libero SoC v2021.2. | A benign error flagged by Libero VHDL array type case with `message ID VHDL-1544` has been fixed.
1074449 | `PF_SRAM_AHBL_AXI` macro-generation issue. | The `PF_SRAM_AHBL_AXI` configurator has been updated to show the DRC for configurations where Max Depth exceeds 65536 with ECC enabled.
942657 | RTG4 back-annotated file generation produces a blank error message. | Issuing the command `configure_tool -name { EXPORTSDF }` in Libero Tcl mode no longer generates a blank error message.
01028331 | For PolarFire and RT PolarFire, Libero does not allow bitstream generation when Security POR is enabled in TAMPER core if default security is selected in the Configure Security tool. | Libero now allows you to export bit streams if POR check for Security is ON in the TAMPER core for default security.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2022.3 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 7-6.Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary | Resolution
--- | ---
PolarFire-, RT PolarFire-, and PolarFire SoC-protected components in the custom security are exported in the SPI bitstream. | If you disable update protection for components (FPGA/SNVM/ENVM) in the Configure Security tool (Update Policy), the components are not exported in the SPI bitstream. For PolarFire SoC, if the OWP protocol is enabled in Configure Security Locks for Production, any component can be exported in SPI bitstream even if the component protected.
Libero SoC crashes when exporting the component description of HDL+ core. | This issue has been fixed.
The stand-alone Program and Debug Linux installer (v2022.3) does not install FlashPro 6 libusb libraries automatically. | The installer has an update for FlashPro 6 driver installation. The Programming and Debug installation is clean on CentOS 7.9, 8.2 and Ubuntu 20.04.3 as super-user.
SmartFusion2, IGLOO2: DAT master bitstream file is incorrect when using Programming Recovery with custom security user settings. Running the ERASE action using this master file does not remove all security settings. | Fixed bit stream generation so that the DAT master bit stream format erases all security settings when running the ERASE action.
PolarFire, RT PolarFire, and PolarFire SoC: SPI bitstreams exported using Libero v2021.1 or earlier cannot be used as SPI bitstream clients in SPI Flash in Libero v2022.2. If they are used, Libero returns the error `Software Version is not available`. | SPI bitstream files exported with older versions of Libero can now be used to create SPI bitstream clients in the SPI Flash tab.
Add TVS capability to SmartDebug. | See section .New TVS Monitor for SmartDebug.
Reset function for O10 and O25 devices is not working properly. | SmartFusion2 and IGLOO2 SerDes simulation models have been updated to reset EPCS and SERDES lane registers with correct register values.
Export SmartDebug data does not support the sNVM-only option. | Standalone programming support of sNVM for the PolarFire SoC family is enabled.
PolarFire, PolarFire SoC, and MSS Configurator: `REFCLK_1_PLL_NW` input is exposed only on the MSS component if DDR uses this reference clock. | The `REFCLK_1_PLL_NW` port is shown if you select the `RTC`/MAC SGMII reference clock source as NW PLL ports `OUT2` or `OUT3` (`REFCLK_1_PLL_NW`).
MSS Configurator allows you to select DDR* configurations that are incompatible with speed grade. | MSS configuration no longer allows DDR4 clocks higher than 666.67 MHz for STD parts.
Interrupt map report is needed. | See section New MSS Interrupt Map Report.
New drop-down list has been added to the Register Access Page in the Debug TRANSCEIVER window. | The Register Access page in the Debug TRANSCEIVER window has a new drop-down list that allows you to show all registers or show only the registers whose read value has been changed. By default, Show All Registers is selected. For more information, see the SmartDebug User Guide .
PolarFire, RT PolarFire, and PolarFire SoC: Libero shows the incorrect warning/summary message `SPI Slave interface is disabled. All SPI pins are disabled` when disabling the SPI Slave interface in Update Policy in the Configure Security tool. | The Libero message no longer says that `SPI pins are disabled` when disabling the SPI Slave interface in the Update Policy in Configure Security tool. The warning was misleading because it said that all SPI pins were disabled. In fact, the SPI master programming, which uses the same pins, was still enabled and functional when SPI Slave programming was disabled. Specifically, the SPI pins (physical pins and SPI controller) were not disabled; only SPI Slave operation was disabled.

Rev: 2025.2

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