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# 5.5 New Silicon Features and Enhancements

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## 5.5.1 PolarFire, RT PolarFire, and PolarFire SoC

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### 5.5.1.1 Generate Memory Map with Mi-V ESS

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The Memory Map functionality has been modified to generate map for the MIV_ESS 2.0.100 version.

### 5.5.1.2 FlashPro 6: SPI-Flash Programming Support for ISSI Flash Memory

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Starting with Libero SoC 2024.1, FlashPro 6 has been enhanced for programming support of IS25WP01G-RILA3.

### 5.5.1.3 PF_IOD_CDR: EYE_MONITOR_WIDTH Parameter Selection

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Starting with Libero SoC 2024.1, the PF_IOD_CDR configurator is updated to include allowing users to adjust the EYE_MONITOR_WIDTH parameter by selecting the window positive and negative side value based on the eye window override option. For usage details, see the latest PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.

### 5.5.1.4 SmartDebug: DDC File Includes Security Component Options DPK, UPK1, and Display DPK (UPK1) in Smart Debug

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Starting with Libero SoC 2024.1, the Libero tool has been enhanced to allow users to control the plaintext pass keys selection to be exported during design handoff for debugging.

### 5.5.1.5 IBIS Model of IND, MIL, TGrade2

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Microchip has added a feature in Libero 2024.1 to export design-specific IBIS models. The following table provides details about the supported FPGA device families, I/O types, and temp-range.

Table 5-4.IBIS Model of IND, Mil, TGrade2
Device Family | I/O Type | Temp-range
--- | --- | ---
PolarFire® PolarFire SoC RT PolarFire | HSIO GPIO | IND MIL TGrade 2
PolarFire SoC | MSSIO | IND MIL TGrade 2

## 5.5.2 RTG4

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### 5.5.2.1 Increase the I/O Capacity per Bank in Designs with Dynamic ODT

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Instantiating the ODT_DYNAMIC macro for an I/O bank no longer causes Libero SoC to mark three extra I/Os on that bank as “reserved.”

Attention: The RTG4_ODT_DYN macro configured for a DDRIO bank has no effect when the FDDR controller is also instantiated on the same DDRIO bank.

Rev: 2026.1

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