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# 1.2 Changes That Address Important Issues

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## 1.2.1 PolarFire, PolarFire SoC, RT PolarFire, and RT PolarFire SoC

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Note: In Libero SoC v2025.2, the timing and power data for the RT PolarFire RTPF500ZT device is at Production status. However, in the timing and power reports, the data source label within Libero SoC v2025.2 currently is displayed as Preliminary. This labeling issue will be corrected in the upcoming Libero SoC v2026.1 release to accurately reflect the Production status.

Additionally, the RTPF500ZT timing data itself has not changed since its initial introduction into Libero SoC v2024.1 release.

### 1.2.1.1 IOD TX Ratio 5, Single-ended Data Output

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Enhanced the Design Rule Check (DRC) process to ensure that the N-side of the IOD pair is correctly restricted and not available for use when configured for single-ended data output.

### 1.2.1.2 Preferred Clock Input

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#### 1.2.1.2.1 MPF500T/TS/TL/TLS, RTPF500T/TS/TL/TLS, RTPF500ZT/TS/TL/TLS

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Enabled the REF_CLK I/O from Transceiver QUAD4 of these devices.

#### 1.2.1.2.2 MPFS460T/TS/TL/TLS, RTPFS460ZT/TS/TL/TLS

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Enabled the REF_CLK I/O from Transceiver QUAD4 of these devices.

#### 1.2.1.2.3 MPFS025T/TS/TL/TLS

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Enabled the preferred clock input I/Os to the two PLLs located at the SE corner of these device.

#### 1.2.1.2.4 Periphery Placement

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Implemented automatic assignment of DLL and PLL blocks when cascaded.

## 1.2.2 PolarFire SoC Standalone MSS Configurator

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### 1.2.2.1 New Physical Memory Protection (PMP) Lockdown Strategies

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The Libero SoC 2025.2 release has the following significant enhancements to the PMP Lockdown Strategies:

- Reorganized the PMP interface layout for more efficient configuration reducing complexity.
- Added an Expert Mode option that allows direct configuration of PMP register settings by advanced users who require direct control over PMP and MPU configurations.

### 1.2.2.2 DDR Partition

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Reorganized the DDR memory partition settings to a dedicated tab, improving usability and making it easier to manage and visualize memory allocation within MSS DDR.

### 1.2.2.3 I²C Voltage

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Expanded the MSS I/O support to operate at 2.5 V when interfacing with I²C peripherals, increasing flexibility and supporting a broader range of external I²C devices.

### 1.2.2.4 CAN Voltage

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Expanded the MSS I/O support to operate at 1.2 V, 1.5 V, 1.8 V, and 2.5 V to enable additional Low Voltage CMOS I/O standards for MSS CAN controller I/O connection to external CAN transceiver, where supported by user board design and transceiver specifications.

### 1.2.2.5 Enhanced Simulation Support for Processor BFM and Tiny QoS AXI Initiator

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The mss_cpu_core can access the non-cache region of MSS DDR through the M14 port of the AXI switch. To mimic the processor behavior during simulation, you can choose to enable either the Processor BFM for the mss_cpu_core or a tiny QoS AXI Initiator, depending on your verification needs.

Rev: 2025.2

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