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# 8.2 Changes that Address Important Issues

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Libero SoC v2022.2 includes changes that address certain important issues.

## 8.2.1 PolarFire, RT PolarFire, and PolarFire SoC

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### 8.2.1.1 PLL Phase Alignment when Using Post-Divider or External Feedback Mode

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The PF_CCC (2.2.214) configurator has been enhanced in the following ways:

- It generates additional soft logic with the PLL to align the phase of output clocks when using Post-Divider or External feedback mode.
- It supports backup clock selection in Post-Divider or External Feedback mode.
- It supports a Reset on Lock selection in Post-VCO mode.
- It generates information about the `LOCKCNT` and PFD frequency.

You must use the `CORERESET_PF` IP core that combines the asynchronous resets from multiple sources such as external GPIO, PLL lock, and `PF_INIT_MONITOR` blocks and synchronously de-asserts the reset to the downstream logic in the user-specified clock domain. For more information on how the `PLL_POWERDOWN_B` signal of the `CORERESET_PF` is connected to the `PLL_POWERDOWN_N_0` signal when the PLL is configured in the Post-VCO feedback mode, see Figure 3-3, Example of PolarFire Initialization, in the PolarFire FPGA and PolarFire SoC FPGA Power-Up and Resets User Guide.

When using the PF_CCC Post-Divider or the external feedback mode, the `PLL_POWERDOWN_N` input must be de-asserted synchronously. The following modification is recommended:

1. Gate the `PLL_POWERDOWN_B` signal of the `CORERESET_PF IP` core by the `DEVICE_INIT_DONE` signal of the `PF_INIT_MONITOR IP` core.
2. Synchronize using two flip-flops to the clock (`REF_CLK_0`) before connecting to the `PLL_POWERDOWN_N_0` signal.

The following figure shows a sample use case of `PF_INIT_MONITOR` and `CORERESET_PF` connected to PF_CCC configured in the Post-Divider or the external feedback mode.

## 8.2.2 RTG4

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### 8.2.2.1 New Timing Constraint Flow Accounts for Global Clock Jitter Automatically

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Libero SoC v2022.2 introduces the automatic computation of clock jitter for Place & Route and Timing analysis. With this feature, you use the `set_input_jitter` constraint to specify the clock jitter for all FPGA primary clock inputs, including RTG4 input buffer jitter and CCC SpaceWire recovered clock jitter on strobe inputs.

The following global clocking resources and clock generation blocks are susceptible to jitter:

- Global clocks nets distributed throughout the FPGA fabric using the dedicated global networks
- External output clocks generated within the FPGA, routed through the global networks, and propagated outside of the FPGA through output buffers
- Clocks generated within the FPGA using blocks such as the internal 50MHz RC Oscillator, PLLs, and the CCC SpaceWire clock recovery circuits
- Strobe input clock when using RTG4 CCC SpaceWire clock recovery circuits
- Other sources, such as RTG4 input buffer jitter

System jitter for the design is estimated based on the count of registers and RAM blocks in the synthesized netlist, as well as the related clock domain switching frequency.

As needed, you can add margin on top of the estimated clock jitter for a domain using the `set_clock_uncertainty` constraint. You can also override the estimated global net clock jitter for the design using the `set_system_jitter` constraint, but this should be done cautiously after carefully reviewing the documents listed below.

A report detailing the clock jitter estimation for each clock domain is generated and shown in the Libero SoC Reports tab. Expanded timing path reports include the clock jitter constraint as an extra line item, if the timing path is affected by clock jitter.

In addition, if Libero detects clock uncertainty constraints in a design, a message prompts you to review your existing timing constraints and consider removing or reducing the manually entered clock uncertainty to avoid unnecessary duplication.

For more information, see the updated RTG4 FPGA datasheet (Rev C or later), Timing Constraints Editor User Guide .

### 8.2.2.2 Changing Default Behavior of GLx_Yx_ARST_N Signals in the CCC Configurator

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The `GLx_Yx_ARST_N` and `GLx_Yx_EN` inputs of RTG4FCCC and RTG4FCCCECALIB cores are now exposed by default to better align with the device documentation. Previously, these inputs were not exposed by default. As stated in the device documentation, the `GLx_Yx_ARST_N` must be forced low upon power-up.

For more information, see the UG0586 RTG4 FPGA Clocking Resources User Guide.

### 8.2.2.3 Added Simulation Support for RTG4 PLL Feedback Delay

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The RTG4-PLL simulation model has been updated to compensate for feedback clock delay. This enhancement enables timing simulation with the PLL feedback delay path included. This is useful when simulating PLL configurations such as external feedback mode (within the FPGA) and the usage of negative CCC/PLL delays. After the PLL LOCK signal asserts, you should observe the internal refclk and feedback signals of same frequency and aligned, which confirms proper PLL compensation with external feedback. Questasim users should use the `-voptargs="+acc"` argument with vsim.

## 8.2.3 SmartFusion2, IGLOO2

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### 8.2.3.1 Prevent Remapping Data from eNVM_1 Memory Block to Cortex-M3 Code Space

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Remapping eNVM data from eNVM_1 memory block to Cortex-M3 Code space is no longer allowed for SmartFusion2 M2S090/150 and IGLOO2 M2GL090/150 devices. If you try to remap M3 to eNVM1, the following error message appears before the MSS System Builder generation.

`Error: Remapping eNVM data to Cortex-M3 Code space from eNVM_1 memory block is not allowed. Please update the eNVM Remap Region Size and eNVM Remap Base Address (Cortex-M3) configuration such that the end address of the eNVM remap region is less than 0x00040000. The remapped region is configured as [0x0003d000:0x00040fff]`

For more information, see the SmartFusion2 Microcontroller Subsystem User Guide.

Rev: 2025.2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.