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High-Performance dsPIC33A Core with Floating-Point Unit, High-Speed ADCs and High-Resolution PWM
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dsPIC33AK128MC106
Product Family
Pin Diagrams
Pinout I/O Descriptions
Terminology Cross Reference
1
Device Overview
2
Guidelines for Getting Started with Digital Signal Controllers
2.1
Basic Connection Requirements
2.2
Decoupling Capacitors
2.3
Master Clear (
MCLR
) Pin
2.4
ICSP Pins
2.5
External Oscillator Pins
2.6
External Oscillator Layout Guidance
2.7
Oscillator Value Conditions on Device Start-up
2.8
Unused I/Os
2.9
Bulk Capacitors
3
CPU
3.1
Architectural Overview
3.2
Register Summary
3.3
Operation
3.4
Prefetch Branch Unit (PBU)
3.5
Performance Monitor Unit (PMU)
3.6
Floating-Point Unit (FPU) Coprocessor
4
Memory Organization
4.1
Device-Specific Information
4.2
Architectural Overview
4.3
Register Summary
4.4
BMX Operation
4.5
Application Example
5
Data Memory
5.1
Device-Specific Information
5.2
Architectural Overview
5.3
Register Summary
5.4
Operation
6
Flash Program Memory
6.1
Device-Specific Information
6.2
Register Summary
6.3
Operation
6.4
Application Example
7
Configuration Bits
7.1
Configuration Register Summary
7.2
Device Calibration and Identification
8
Security Module
8.1
Architectural Overview
8.2
Register Summary
8.3
Flash Memory Map
8.4
Device Locking
8.5
Flash Protection Regions
8.6
Peripheral Access Controller (PAC)
9
Resets
9.1
Architectural Overview
9.2
Register Summary
9.3
Operation
9.4
Application Example
9.5
Effects of Reset
10
Interrupt Controller
10.1
Device-Specific Information
10.2
Architectural Overview
10.3
Interrupt Vector Table
10.4
Register Summary
10.5
Operation
10.6
Interrupt Control and Status Registers
10.7
Priority
10.8
Interrupt Sequence
10.9
Non-Maskable Traps
10.10
Disabling Interrupts
10.11
External Interrupt Requests
10.12
Wake-Up From Sleep, Idle
10.13
Interrupt Processing Timing
10.14
Interrupt Setup Procedures
11
I/O Ports with Edge Detect
11.1
Device-Specific Information
11.2
Architectural Overview
11.3
Register Summary
11.4
Operation
11.5
Application Example
11.6
Interrupts
11.7
Power-Saving Modes
11.8
Effects of Various Resets
12
Oscillator and Clocking Module
12.1
Device-Specific Information
12.2
Architectural Overview
12.3
Register Summary
12.4
Operation
13
Direct Memory Access (DMA) Controller
13.1
Device-Specific Information
13.2
Architectural Overview
13.3
Register Summary
13.4
Operation
13.5
Application Examples
13.6
Interrupts
13.7
Power-Saving Modes
14
High-Resolution Pulse-Width Modulation (PWM)
14.1
Device-Specific Information
14.2
Architectural Overview
14.3
Register Summary
14.4
Operation
14.5
Application Examples
14.6
Interrupts
14.7
Power-Saving Modes
15
High-Speed, Low Latency ADC
15.1
Device-Specific Information
15.2
Architectural Overview
15.3
Register Summary
15.4
Operation
15.5
Application Examples
15.6
Effects of Reset
16
High-Speed Analog Comparator with Slope Compensation DAC
16.1
Device-Specific Information
16.2
Architectural Overview
16.3
Register Summary
16.4
Operation
16.5
Application Examples
17
Quadrature Encoder Interface (QEI)
17.1
Device-Specific Information
17.2
Architectural Overview
17.3
Register Summary
17.4
Operation
17.5
Application Example
17.6
Interrupts
17.7
Power-Saving Modes
18
Universal Asynchronous Receiver Transmitter (UART)
18.1
Device-Specific Information
18.2
Architectural Overview
18.3
Register Summary
18.4
Operation
18.5
Application Examples
18.6
Interrupts
18.7
Power-Saving Modes
19
Serial Peripheral Interface (SPI)
19.1
Device-Specific Information
19.2
Architectural Overview
19.3
Register Summary
19.4
Operation
19.5
Interrupts
19.6
Power-Saving and Debug Modes
20
Inter-Integrated Circuit (I
2
C)
20.1
Device-Specific Information
20.2
Architectural Overview
20.3
I2C System Overview
20.4
Register Summary
20.5
Operation
20.6
Application Examples
20.7
Interrupts
20.8
Operation in Power-Saving Modes
21
Single-Edge Nibble Transmission (SENT)
21.1
Device-Specific Information
21.2
Architectural Overview
21.3
Register Summary
21.4
Operation
21.5
Application Examples
21.6
Interrupts
21.7
Power-Saving Modes
21.8
Effects of a Reset
22
Bidirectional Serial Synchronous (BiSS) Module
22.1
Device-Specific Information
22.2
Architectural Overview
22
Register Summary
22.3
Operation
22.4
Application Examples
22.5
Interrupts
22.6
Power Saving Modes
22.7
Terminology
23
Timer1
23.1
Device-Specific Information
23.2
Architectural Overview
23.3
Register Summary
23.4
Operation
23.5
Interrupts
23.6
Power-Saving Modes
23.7
Effects of Various Resets
24
Single-Output Capture/Compare/PWM/Timer Modules (SCCP)
24.1
Device-Specific Information
24.2
Architectural Overview
24.3
Register Summary
24.4
Operation
24.5
Power-Saving Modes
24.6
Effects of a Reset
25
Configurable Logic Cell (CLC)
25.1
Device-Specific Information
25.2
Architecture
25.3
Register Summary
25.4
Operation
25.5
CLC Application Example
25.6
CLC Interrupts
25.7
Power-Saving Modes
26
Peripheral Trigger Generator (PTG)
26.1
Device-Specific Information
26.2
Architectural Overview
26.3
Register Summary
26.4
Operation
26.5
Application Examples
26.6
Interrupts
26.7
Power-Saving Modes
27
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
27.1
Architectural Overview
27.2
Register Summary
27.3
Operation
27.4
Application Examples
27.5
Power-Saving Modes
28
Current Bias Generator (CBG)
28.1
Device-Specific Information
28.2
Architectural Overview
28.3
Current Bias Generator Control Register
Current Bias Generator Control Register
28.4
Operation
28.5
Application Examples
28.6
Interrupts
28.7
Power-Saving Modes
28.8
Effects of a Reset
29
Operational Amplifier (Op Amp)
29.1
Device-Specific Information
29.2
Architectural Overview
29.3
Register Summary
29.4
Operations
29.5
Op Amp Application Examples
30
Watchdog Timer (WDT)
30.1
Device-Specific Information
30.2
Architectural Overview
30.3
Register Summary
30.4
Operation
30.5
Watchdog Timer Reset
30.6
Power-Saving Modes
30.7
WDT Generic Trap
30.8
WDT Sample Configuration
31
Deadman Timer (DMT)
31.1
Architectural Overview
31.2
Register Summary
31.3
Operation
32
Device Power-Saving Modes
32.1
Architectural Overview
32.2
Register Summary
32.3
Operation
33
JTAG Interface
34
In-Circuit Debugger
35
Instruction Set Summary
36
Development Support
37
Electrical Characteristics
37.1
DC Characteristics
37.2
AC Characteristics and Timing Parameters
38
High-Temperature Electrical Characteristics
39
Packaging Information
39.1
Package Marking Information
39.2
Package Details
40
Revision History
41
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature
