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PIC16F18013/14/23/24 Full-Featured 8/14-Pin Microcontrollers
Introduction
PIC16F18076 Family Summary
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
Block Diagram
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC16F18076 Microcontrollers
4.1 Basic Connection Requirements
4.2 Power Supply Pins
4.3 Master Clear (MCLR) Pin
4.4 In-Circuit Serial Programming™ (ICSP™) Pins
4.5 Unused I/Os
5 Register and Bit Naming Conventions
5.1 Register Names
5.2 Bit Names
5.3 Register and Bit Naming Exceptions
6 Register Legend
7 Enhanced Mid-Range CPU
7.1 Automatic Interrupt Context Saving
7.2 16-Level Stack with Overflow and Underflow
7.3 File Select Registers
7.4 Instruction Set
8 Device Configuration
8.1 Configuration Words
8.2 Code Protection
8.3 Write Protection
8.4 User ID
8.5 Device ID and Revision ID
8.6 Register Definitions: Configuration Settings
8.7 Register Definitions: Device ID and Revision ID
9 Memory Organization
9.1 Program Memory Organization
9.2 Data Memory Organization
9.3 STATUS Register
9.4 PCL and PCLATH
9.5 Stack
9.6 Indirect Addressing
9.7 Register Definitions: Memory Organization
9.8 Register Summary - Memory Organization
10 Resets
10.1 Power-on Reset (POR)
10.2 Brown-out Reset (BOR)
10.3 MCLR Reset
10.4 Watchdog Timer (WDT) Reset
10.5 RESET Instruction
10.6 Stack Overflow/Underflow Reset
10.7 Power-Up Timer (PWRT)
10.8 Start-Up Sequence
10.9 Memory Execution Violation
10.10 Determining the Cause of a Reset
10.11 Power Control (PCONx) Register
10.12 Register Definitions: Power Control
10.13 Register Summary - Power Control
11 OSC - Oscillator Module
11.1 Clock Source Types
11.2 Active Clock Tuning (ACT)
11.3 Register Definitions: Oscillator Module
11.4 Register Summary - Oscillator Module
12 INT - Interrupts
12.1 Overview
12.2 INTCON Register
12.3 PIE Registers
12.4 PIR Registers
12.5 Operation
12.6 Interrupt Latency
12.7 Interrupts During Sleep
12.8 INT Pin
12.9 Automatic Context Saving
12.10 Register Definitions: Interrupt Control
12.11 Register Summary - Interrupt Control
13 Sleep Mode
13.1 Sleep Mode Operation
14 WDT - Watchdog Timer
14.1 Selectable Clock Sources
14.2 WDT Operating Modes
14.3 WDT Time-Out Period
14.4 Clearing the WDT
14.5 WDT Operation During Sleep
14.6 Register Definitions: WDT Control
14.7 Register Summary - WDT Control
15 NVM - Nonvolatile Memory Control
15.1 Program Flash Memory (PFM)
15.2 Data Flash Memory (DFM)
15.3 Register Definitions: Nonvolatile Memory Control
15.4 Register Summary - NVM Control
16 I/O Ports
16.1 Overview
16.2 PORTx - Data Register
16.3 LATx - Output Latch
16.4 TRISx - Direction Control
16.5 ANSELx - Analog Control
16.6 WPUx - Weak Pull-Up Control
16.7 INLVLx - Input Threshold Control
16.8 SLRCONx - Slew Rate Control
16.9 ODCONx - Open-Drain Control
16.10 Edge Selectable Interrupt-on-Change
16.11 I2C Pad Control
16.12 I/O Priorities
16.13 MCLR/VPP/RA3 Pin
16.14 Register Definitions: Port Control
16.15 Register Summary - I/O Ports
17 IOC - Interrupt-on-Change
17.1 Overview
17.2 Enabling the Module
17.3 Individual Pin Configuration
17.4 Interrupt Flags
17.5 Clearing Interrupt Flags
17.6 Operation in Sleep
17.7 Register Definitions: Interrupt-on-Change Control
17.8 Register Summary - Interrupt-on-Change
18 PPS - Peripheral Pin Select Module
18.1 Overview
18.2 PPS Inputs
18.3 PPS Outputs
18.4 Bidirectional Pins
18.5 PPS Lock
18.6 Operation During Sleep
18.7 Effects of a Reset
18.8 Register Definitions: Peripheral Pin Select (PPS)
18.9 Register Summary - Peripheral Pin Select Module
19 TMR0 - Timer0 Module
19.1 Timer0 Operation
19.2 Clock Selection
19.3 Timer0 Output and Interrupt
19.4 Operation During Sleep
19.5 Register Definitions: Timer0 Control
19.6 Register Summary - Timer0
20 TMR1 - Timer1 Module with Gate Control
20.1 Timer1 Operation
20.2 Clock Source Selection
20.3 Timer1 Prescaler
20.4 Secondary Oscillator
20.5 Timer1 Operation in Asynchronous Counter Mode
20.6 Timer1 16-Bit Read/Write Mode
20.7 Timer1 Gate
20.8 Timer1 Interrupt
20.9 Timer1 Operation During Sleep
20.10 CCP Capture/Compare Time Base
20.11 CCP Special Event Trigger
20.12 Register Definitions: Timer1 Control
20.13 Register Summary - Timer1
21 TMR2 - Timer2 Module
21.1 Timer2 Operation
21.2 Timer2 Output
21.3 External Reset Sources
21.4 Timer2 Interrupt
21.5 PSYNC Bit
21.6 CSYNC Bit
21.7 Operating Modes
21.8 Operation Examples
21.9 Timer2 Operation During Sleep
21.10 Register Definitions: Timer2 Control
21.11 Register Summary - Timer2
22 NCO - Numerically Controlled Oscillator Module
22.1 NCO Operation
22.2 Fixed Duty Cycle Mode
22.3 Pulse Frequency Mode
22.4 Output Polarity Control
22.5 Interrupts
22.6 Effects of a Reset
22.7 Operation in Sleep
22.8 Register Definitions: NCO
22.9 Register Summary - NCO
23 CCP - Capture/Compare/PWM Module
23.1 CCP Module Configuration
23.2 Capture Mode
23.3 Compare Mode
23.4 PWM Overview
23.5 Register Definitions: CCP Control
23.6 Register Summary - CCP Control
24 Capture, Compare, and PWM Timers Selection
24.1 Register Definitions: Capture, Compare, and PWM Timers Selection
24.2 Register Summary - Capture, Compare, and PWM Timers Selection
25 PWM - Pulse-Width Modulation
25.1 Fundamental Operation
25.2 PWM Output Polarity
25.3 PWM Period
25.4 PWM Duty Cycle
25.5 PWM Resolution
25.6 Operation in Sleep Mode
25.7 Changes in System Clock Frequency
25.8 Effects of Reset
25.9 Setup for PWM Operation Using PWMx Output Pins
25.10 Setup for PWM Operation to Other Device Peripherals
25.11 Register Definitions: PWM Control
25.12 Register Summary - PWM
26 PWM Timers Selection
26.1 Register Definitions: Capture, Compare, and PWM Timers Selection
26.2 Register Summary - Capture, Compare, and PWM Timers Selection
27 CLC - Configurable Logic Cell
27.1 CLC Setup
27.2 CLC Interrupts
27.3 Effects of a Reset
27.4 Output Mirror Copies
27.5 Operation During Sleep
27.6 CLC Setup Steps
27.7 Register Overlay
27.8 Register Definitions: Configurable Logic Cell
27.9 Register Summary - CLC Control
28 MSSP - Host Synchronous Serial Port Module
28.1 SPI Mode Overview
28.2 I2C Mode Overview
28.3 Baud Rate Generator
28.4 Register Definitions: MSSP Control
28.5 Register Summary - MSSP Control
29 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
29.1 EUSART Asynchronous Mode
29.2 Clock Accuracy with Asynchronous Operation
29.3 EUSART Baud Rate Generator (BRG)
29.4 EUSART Synchronous Mode
29.5 EUSART Operation During Sleep
29.6 Register Definitions: EUSART Control
29.7 Register Summary - EUSART
30 ADC - Analog-to-Digital Converter with Computation Module
30.1 ADC Configuration
30.2 ADC Operation
30.3 ADC Acquisition Requirements
30.4 Computation Operation
30.5 Register Definitions: ADC Control
30.6 Register Summary - ADC
31 DAC - Digital-to-Analog Converter Module
31.1 Output Voltage Selection
31.2 Ratiometric Output Level
31.3 Buffered DAC Output Range Selection
31.4 Operation During Sleep
31.5 Effects of a Reset
31.6 Register Definitions: DAC Control
31.7 Register Summary - DAC
32 CMP - Comparator Module
32.1 Comparator Overview
32.2 Comparator Control
32.3 Comparator Hysteresis
32.4 Comparator Interrupt
32.5 Comparator Positive Input Selection
32.6 Comparator Negative Input Selection
32.7 Comparator Response Time
32.8 Analog Input Connection Considerations
32.9 Operation in Sleep Mode
32.10 ADC Auto-Trigger Source
32.11 Register Definitions: Comparator Control
32.12 Register Summary - Comparator
33 FVR - Fixed Voltage Reference
33.1 Independent Gain Amplifiers
33.2 FVR Stabilization Period
33.3 Register Definitions: FVR
33.4 Register Summary - FVR
34 Temperature Indicator Module
34.1 Module Operation
34.2 Temperature Calculation
34.3 ADC Acquisition Time
34.4 Register Definitions: Temperature Indicator
34.5 Register Summary - Temperature Indicator
35 ZCD - Zero-Cross Detection Module
35.1 External Resistor Selection
35.2 ZCD Logic Output
35.3 ZCD Logic Polarity
35.4 ZCD Interrupts
35.5 Correction for ZCPINV Offset
35.6 Handling VPEAK Variations
35.7 Operation During Sleep
35.8 Effects of a Reset
35.9 Disabling the ZCD Module
35.10 Register Definitions: ZCD Control
35.11 Register Summary - ZCD
36 Charge Pump
36.1 Manually Enabled
36.2 Automatically Enabled
36.3 Disabled
36.4 Charge Pump Oscillator
36.5 Charge Pump Threshold
36.6 Charge Pump Ready
36.7 Register Definitions: Charge Pump
36.8 Register Summary - Charge Pump
37 Instruction Set Summary
37.1 Read-Modify-Write Operations
37.2 Standard Instruction Set
38 ICSP™ - In-Circuit Serial Programming™
38.1 High-Voltage Programming Entry Mode
38.2 Low-Voltage Programming Entry Mode
38.3 Common Programming Interfaces
39 Register Summary
40 Electrical Specifications
40.1 Absolute Maximum Ratings(†)
40.2 Standard Operating Conditions
40.3 DC Characteristics
40.4 AC Characteristics
41 DC and AC Characteristics Graphs and Tables
41.1 10-Bit Analog-to-Digital Converter (ADC) Graphs
41.2 Brown-Out Reset Graphs
41.3 Comparator Graphs
41.4 8-Bit Digital-to-Analog Converter (DAC) Graphs
41.5 Fixed Voltage Reference Graphs
41.6 HFINTOSC Error Graphs
41.7 HFINTOSC Wake From Sleep Graphs
41.8 I/O Rise/Fall Times Graphs
41.9 IDD Graphs
41.10 Input Buffer Graphs
41.11 IPD Graphs
41.12 LFINTOSC Graphs
41.13 OSCTUNE Graphs
41.14 Power-On Reset Graphs
41.15 VOH - VOL Graphs
41.16 Watchdog Timer Graphs
41.17 Weak Pull-Up Graphs
42 Packaging Information
42.1 Package Details
43 Appendix A: Revision History
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