Jump to main content
High-Performance 32-bit MCU
High-Performance 32-bit MCUs with Floating-Point Unit and High-Speed ADCs
1 PIC32AK1216GC41064 Product Family
1.1 Pin Diagrams
1.2 Pin Diagrams
1.3 Pin Diagrams
2 Pinout I/O Descriptions
3 Guidelines for Getting Started with Digital Signal Controllers
3.1 Basic Connection Requirements
3.2 Decoupling Capacitors
3.3 Master Clear (MCLR) Pin
3.4 ICSP Pins
3.5 External Oscillator Pins
3.6 External Oscillator Layout Guidance
3.7 Oscillator Value Conditions on Device Start-up
3.8 Unused I/Os
3.9 Bulk Capacitors
4 Ordering Information
5 Device Overview
6 CPU
6.1 Architectural Overview
6.2 Register Summary
6.3 Operation
6.4 Prefetch Branch Unit (PBU)
6.5 Performance Monitor Unit (PMU)
6.6 Floating-Point Unit (FPU) Coprocessor
7 Memory Organization
7.1 Device-Specific Information
7.2 Architectural Overview
7.3 Register Summary
7.4 BMX Operation
7.5 Application Example
8 Data Memory
8.1 Device-Specific Information
8.2 Architectural Overview
8.3 Register Summary
8.4 Operation
9 Flash Program Memory
9.1 Device-Specific Information
9.2 Register Summary
9.3 Operation
9.4 Application Example
10 Configuration Bits
10.1 Configuration Register Summary
10.2 Device Calibration and Identification
11 Security Module
11.1 Architectural Overview
11.2 Register Summary
11.3 Flash Memory Map
11.4 Device Locking
11.5 Flash Protection Regions
11.6 Peripheral Access Controller (PAC)
12 Resets
12.1 Architectural Overview
12.2 Register Summary
12.3 Operation
12.4 Application Example
12.5 Effects of Reset
13 Interrupt Controller
13.1 Device-Specific Information
13.2 Architectural Overview
13.3 Interrupt Vector Table
13.4 Register Summary
13.5 Operation
13.6 Interrupt Control and Status Registers
13.7 Priority
13.8 Interrupt Sequence
13.9 Non-Maskable Traps
13.10 Disabling Interrupts
13.11 External Interrupt Requests
13.12 Wake-Up From Sleep, Idle
13.13 Interrupt Processing Timing
13.14 Interrupt Setup Procedures
14 I/O Ports with Edge Detect
14.1 Device-Specific Information
14.2 Architectural Overview
14.3 Register Summary
14.4 Operation
14.5 Application Example
14.6 Interrupts
14.7 Operation in Power-Saving Modes
14.8 Effects of Various Resets
15 Oscillator and Clocking Module
15.1 Device-Specific Information
15.2 Architectural Overview
15.3 Register Summary
15.4 Operation
16 Direct Memory Access (DMA) Controller
16.1 Device-Specific Information
16.2 Architectural Overview
16.3 Register Summary
16.4 Operation
16.5 Application Examples
16.6 DMA Interrupts
16.7 Operation During Sleep and Idle Modes
17 High-Resolution Pulse-Width Modulation (PWM)
17.1 Device-Specific Information
17.2 Architectural Overview
17.3 Register Summary
17.4 Operation
17.5 Application Examples
17.6 Interrupts
17.7 Operation in Power-Saving Modes
18 High-Speed, Low Latency ADC
18.1 Device-Specific Information
18.2 Architectural Overview
18.3 Register Summary
18.4 Operation
18.5 Application Examples
18.6 Effects of Reset
19 High-Speed Analog Comparator with Slope Compensation DAC
19.1 Device-Specific Information
19.2 Architectural Overview
19.3 Register Summary
19.4 Operation
19.5 Application Examples
20 Quadrature Encoder Interface (QEI)
20.1 Device-Specific Information
20.2 Architectural Overview
20.3 Register Summary
20.4 Operation
20.5 Application Example
20.6 Interrupts
20.7 QEI Operation in Power-Saving Modes
21 Universal Asynchronous Receiver Transmitter (UART)
21.1 Device-Specific Information
21.2 Architectural Overview
21.3 Register Summary
21.4 Operation
21.5 Application Examples
21.6 Interrupts
21.7 Power-Saving Modes
22 Serial Peripheral Interface (SPI)
22.1 Device-Specific Information
22.2 Architectural Overview
22.3 Register Summary
22.4 Operation
22.5 Interrupts
22.6 Operation in Power-Saving and Debug Modes
23 Inter-Integrated Circuit (I2C)
23.1 Device-Specific Information
23.2 Architectural Overview
23.3 I2C System Overview
23.4 Register Summary
23.5 Operation
23.6 Application Examples
23.7 Interrupts
23.8 Operation in Power-Saving Modes
24 Single-Edge Nibble Transmission (SENT)
24.1 Device-Specific Information
24.2 Architectural Overview
24.3 Register Summary
24.4 Operation
24.5 Application Examples
24.6 Interrupts
24.7 Operation in Power-Saving Modes
24.8 Effects of a Reset
25 Bidirectional Serial Synchronous (BiSS) Module
25.1 Device-Specific Information
25.2 Architectural Overview
25 Register Summary
25.3 Operation
25.4 Application Examples
25.5 Interrupts
25.6 Power Saving Modes
25.7 Terminology
26 Timer1
26.1 Device-Specific Information
26.2 Architectural Overview
26.3 Register Summary
26.4 Operation
26.5 Interrupts
26.6 Operation in Power-Saving Modes
26.7 Effects of Various Resets
27 Single-Output Capture/Compare/PWM/Timer Modules (SCCP)
27.1 Device-Specific Information
27.2 Architectural Overview
27.3 Register Summary
27.4 Operation
27.5 Operation During Sleep and Idle Modes
27.6 Effects of a Reset
28 Configurable Logic Cell (CLC)
28.1 Device-Specific Information
28.2 Architecture
28.3 Register Summary
28.4 Operation
28.5 CLC Application Example
28.6 CLC Interrupts
28.7 Operation in Power-Saving Modes
29 Peripheral Trigger Generator (PTG)
29.1 Device-Specific Information
29.2 Architectural Overview
29.3 Register Summary
29.4 Operation
29.5 Application Examples
29.6 Interrupts
29.7 Power-Saving Modes
30 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
30.1 Architectural Overview
30.2 Register Summary
30.3 Operation
30.4 Application Examples
30.5 CRC Operation in Power Saving Modes
31 Current Bias Generator (CBG)
31.1 Device-Specific Information
31.2 Architectural Overview
31.3 Current Bias Generator Control Register
Current Bias Generator Control Register
31.4 Operation
31.5 Application Examples
31.6 Interrupts
31.7 Operating in Power-Saving Modes
31.8 Effects of a Reset
32 Operational Amplifier (Op Amp)
32.1 Device-Specific Information
32.2 Architectural Overview
32.3 Register Summary
32.4 Operations
32.5 Op Amp Application Examples
33 Watchdog Timer (WDT)
33.1 Device-Specific Information
33.2 Architectural Overview
33.3 Register Summary
33.4 Operation
33.5 Watchdog Timer Reset
33.6 Operation of Watchdog Timer in Sleep/Idle Modes
33.7 WDT Generic Trap
33.8 WDT Sample Configuration
34 Deadman Timer (DMT)
34.1 Architectural Overview
34.2 Register Summary
34.3 Operation
35 Power-Saving Modes
35.1 Architectural Overview
35.2 Register Summary
35.3 Operation
36 JTAG Interface
37 In-Circuit Debugger
38 Instruction Set Summary
39 Development Support
40 Electrical Characteristics
40.1 DC Characteristics
40.2 AC Characteristics and Timing Parameters
41 Packaging Information
41.1 Package Marking Information
41.2 Package Details
42 Revision History
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.