10BASE-T1S Ethernet PHY Transceiver LAN8670/1/2

1.1 General Terms

1.2 Buffer Types

1.3 Register Bit Types

1.4 Reference Documents

2.1 General Description

2.2 The LAN8670/1/2 Family

2.3 Example Systems

3 Pin Description and Configuration

3.1 LAN8670 Pin Assignments

3.2 LAN8671 Pin Assignments

3.3 LAN8672 Pin Assignments

3.4 Pin Descriptions

3.5 Configuration Straps

3.6 Pin Configuration

4 Functional Descriptions

4.1 Media Independent Interface (MII)

4.2 Reduced Media Independent Interface (RMII)

4.3 Serial Management Interface (SMI)

4.4 Interrupt Management

4.6 Initialization

4.7 Clock Manager

4.8 Physical Layer Collision Avoidance (PLCA)

4.9 Application Controlled Media Access (ACMA)

4.10 Credit Based Traffic Shaping

4.11 Configuration Protection

4.12 Time Synchronization

4.13 Sleep Mode

4.14 Signal Quality Indicator (SQI)

4.15 Cable Fault Diagnostics

4.16 Safety Notifications

5 Register Descriptions

5.1 SMI Basic Control and Status Registers

5.2 PMA/PMD Registers

5.3 PCS Registers

5.4 Miscellaneous Registers

6 Application Information

6.1 MII Connectivity

6.2 RMII Connectivity with Reference Clock

6.3 System Configuration without Sleep Mode

6.4 Power Connectivity

6.5 Electromagnetic Compatibility (EMC) Considerations

6.6 PLCA Collision Detection

6.7 Crystal Oscillator Selection

6.8 Reference Schematics

7 Operational Characteristics

7.1 Absolute Maximum Ratings

7.2 Operating Conditions

7.3 Power Consumption

7.4 Package Thermal Specifications

7.5 DC Specifications (other than 10BASE-T1S PMA)

7.6 AC Specifications

7.7 Clock Circuit

8 Packaging Information

8.1 32-VQFN (LAN8670 Only)

8.2 24-VQFN (LAN8671 Only)

8.3 36-VQFN (LAN8672 Only)

9 Package Marking Information

Product Identification System

Data Sheet Revision History

Microchip Information

Microchip Devices Code Protection Feature

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