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PL360 Host Controller
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Introduction
Features
1
PL360 Host Controller Architecture
1.1
PL360 Host Controller File Structure
1.2
Application Interface (API)
1.3
PLC Stack Wrapper
1.4
Add-ons
1.5
Bootloader
1.6
Hardware Abstraction Layer (HAL)
1.7
Sleep Mode
1.8
Debug Mode
2
PL360 System Architecture
2.1
Block Diagram
2.2
Bootloader
2.3
PL360 Memory
2.4
PL360 Drivers
2.5
PHY PLC Service
2.6
PHY Host Application
3
Brief about ASF
4
Initialization Example
4.1
Init Controller Descriptor
4.2
Set Controller Callbacks
4.3
Enable Controller
4.4
PLC Event Handling
4.5
Code Example
5
Configuration
5.1
Configure Application
5.2
Configure Secure Mode
5.3
Zero-Crossing Configuration
5.4
Transmission Coupling Configuration
6
Host Interface Management
6.1
Message Transmission
6.2
Message Reception
7
SPI Protocol
7.1
Boot Command Format
7.2
Boot Response Format
7.3
Firmware Command Format
7.4
Firmware Response Format
7.5
GUID-B5BD2962-23B1-4FBE-9D42-64AB9C224384-high.png
7.6
Firmware Data Memory Regions
7.7
Message Flow for Basic Transactions
8
Example Applications
8.1
PHY Examples
9
Supported Platforms
9.1
Supported MCU Families
9.2
Supported PLC Devices
9.3
Supported Boards
10
PL360 Host Controller API
10.1
Common PHY API
10.2
G3 PHY API
10.3
PRIME PHY API
11
Abbreviations
12
References
13
Revision History
13.1
Rev A – 03/2018
13.2
Rev B - 10/2018
13.3
Rev C - 04/2019
13.4
Rev D - 07/2019
13.5
Rev E - 08/2020
13.6
Rev F - 04/2022
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