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AVR32/16DU14/20/28/32 Preliminary Data Sheet
Introduction
Features
AVR® DU Family Overview
1 Memory Overview
2 Peripheral Overview
Security Concept
1 Block Diagram
2 Pinout
2.1 14-Pin SOIC
2.2 20-Pin SSOP
2.3 20-Pin VQFN
2.4 28-Pin SPDIP and SSOP
2.5 28-Pin VQFN
2.6 32-Pin TQFP and VQFN
3 I/O Multiplexing and Considerations
3.1 I/O Multiplexing
4 Hardware Guidelines
4.1 General Guidelines
4.2 Connection for Power Supply
4.3 Connection for RESET
4.4 Connection for UPDI Programming
4.5 Connection for External Voltage Reference
5 Power Supply
5.1 Power Domains
5.2 Voltage Regulator
5.3 Power-Up
5.4 USB Power Supply Configurations
6 AVR® CPU
6.1 Features
6.2 Overview
6.3 Architecture
6.4 Functional Description
6.5 Register Summary
6.6 Register Description
7 Memories
7.1 Overview
7.2 Memory Map
7.3 In-System Reprogrammable Flash Program Memory
7.4 Program and Debug Interface Disable (PDID)
7.5 SRAM Data Memory
7.6 EEPROM Data Memory
7.7 SIGROW - Signature Row
7.8 BOOTROW - Boot Row
7.9 USERROW - User Row
7.10 FUSE - Configuration and User Fuses
7.11 LOCK - Memory Sections Access Protection
7.12 I/O Memory
8 Peripherals and Architecture
8.1 Peripheral Address Map
8.2 Interrupt Vector Mapping
8.3 SYSCFG - System Configuration
9 GPR - General Purpose Registers
9.1 Register Summary
9.2 Register Description
10 NVMCTRL - Nonvolatile Memory Controller
10.1 Features
10.2 Overview
10.3 Functional Description
10.4 Register Summary
10.5 Register Description
11 CLKCTRL - Clock Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary
11.5 Register Description
12 SLPCTRL - Sleep Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
13 RSTCTRL - Reset Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary
13.5 Register Description
14 CPUINT - CPU Interrupt Controller
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary
14.5 Register Description
15 EVSYS - Event System
15.1 Features
15.2 Overview
15.3 Functional Description
15.4 Register Summary
15.5 Register Description
16 PORTMUX - Port Multiplexer
16.1 Overview
16.2 Register Summary
16.3 Register Description
17 PORT - I/O Pin Configuration
17.1 Features
17.2 Overview
17.3 Functional Description
17.4 Register Summary - PORTx
17.5 Register Description - PORTx
17.6 Register Summary - VPORTx
17.7 Register Description - VPORTx
18 BOD - Brown-out Detector
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary
18.5 Register Description
19 VREF - Voltage Reference
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary
19.5 Register Description
20 WDT - Watchdog Timer
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary
20.5 Register Description
21 RTC - Real-Time Counter
21.1 Features
21.2 Overview
21.3 Clocks
21.4 RTC Functional Description
21.5 PIT Functional Description
21.6 Crystal Error Correction
21.7 Events
21.8 Interrupts
21.9 Sleep Mode Operation
21.10 Synchronization
21.11 Debug Operation
21.12 Register Summary
21.13 Register Description
22 TCA - 16-bit Timer/Counter Type A
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary - Normal Mode
22.5 Register Description - Normal Mode
22.6 Register Summary - Split Mode
22.7 Register Description - Split Mode
23 TCB - 16-Bit Timer/Counter Type B
23.1 Features
23.2 Overview
23.3 Functional Description
23.4 Register Summary
23.5 Register Description
24 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
24.1 Features
24.2 Overview
24.3 Functional Description
24.4 Register Summary
24.5 Register Description
25 SPI - Serial Peripheral Interface
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary
25.5 Register Description
26 TWI - Two-Wire Interface
26.1 Features
26.2 Overview
26.3 Functional Description
26.4 Register Summary
26.5 Register Description
27 USB - Universal Serial Bus Device Controller
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary - USBn
27.5 Register Description - USBn
27.6 Register Summary - USB_EP - Control, Bulk and Interrupt Endpoints
27.7 Register Description - USB_EP - Control, Bulk and Interrupt Endpoints
28 CRCSCAN - Cyclic Redundancy Check Memory Scan
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 CCL - Configurable Custom Logic
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary
29.5 Register Description
30 AC - Analog Comparator
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary
30.5 Register Description
31 ADC - Analog-to-Digital Converter
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary
31.5 Register Description
32 UPDI - Unified Program and Debug Interface
32.1 Features
32.2 Overview
32.3 Functional Description
32.4 Register Summary
32.5 Register Description
33 Instruction Set Summary
34 Ordering Information
35 Package Drawings
35.1 Online Package Drawings
35.2 Package Marking Information
35.3 14-Pin SOIC
35.4 20-Pin SSOP
35.5 20-Pin VQFN
35.6 28-Pin SPDIP
35.7 28-Pin SSOP
35.8 28-Pin VQFN
35.9 32-Pin TQFP
35.10 32-Pin VQFN
36 Electrical Characteristics
36.1 Disclaimer
36.2 Absolute Maximum Ratings
36.3 Standard Operating Conditions
36.4 Supply Voltage
36.5 Power Consumption
36.6 Peripherals Power Consumption
36.7 I/O Pins
36.8 Memory Programming Specifications
36.9 Thermal Specifications
36.10 CLKCTRL
36.11 RSTCTRL
36.12 VREF
36.13 USART
36.14 SPI
36.15 TWI
36.16 ADC
36.17 AC
36.18 UPDI
37 Characteristics Graphs
38 Data Sheet Revision History
38.1 Revision History
Microchip Information
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Product Identification System
Microchip Devices Code Protection Feature
Legal Notice
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