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AVR32SD20/28/32 Preliminary Data Sheet
Introduction
Features
AVR® SD Family Overview
1 Memory Overview
2 Peripheral Overview
1 Functional Safety Concept
1.1 Error Controller
1.2 Dual CPU Core
1.3 ECC Protection
1.4 Data Bus Parity
1.5 Clock Protection
1.6 Voltage Regulator Monitor
1.7 Watchdogs
1.8 Stack Monitor
1.9 Redundancy
1.10 Integrity Checks
2 Security Concept
3 Block Diagram
4 Pinout
4.1 20-Pin SSOP
4.2 28-Pin VQFN
4.3 28-Pin SSOP and SPDIP
4.4 32-Pin VQFN and TQFP
5 I/O Multiplexing and Considerations
5.1 I/O Multiplexing
6 Hardware Guidelines
6.1 General Guidelines
6.2 Connection for Power Supply
6.3 Connection for RESET
6.4 Connection for UPDI Programming
6.5 Connecting External Crystal Oscillators
6.6 Connection for External Voltage Reference
7 Power Supply
7.1 Power Domains
7.2 Voltage Regulator
7.3 Power-Up
8 Conventions
8.1 Numerical Notation
8.2 Memory Size and Type
8.3 Frequency and Time
8.4 Registers and Bits
8.5 ADC Parameter Definitions
9 BOOTROM - Boot ROM Code
9.1 Overview
9.2 Features
9.3 Functional Description
10 AVR® CPU
10.1 Features
10.2 Overview
10.3 Architecture
10.4 Functional Description
10.5 Functional Safety
10.6 Register Summary
10.7 Register Description
11 BUSMATRIX - Bus Matrix
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Functional Safety
12 Memories
12.1 Overview
12.2 Memory Map
12.3 In-System Reprogrammable Flash Program Memory
12.4 Program and Debug Interface Disable (PDID)
12.5 SRAM Data Memory
12.6 EEPROM Data Memory
12.7 SIGROW - Signature Row
12.8 BOOTROW - Boot Row
12.9 USERROW - User Row
12.10 FUSE - Configuration and User Fuses
12.11 LOCK - Memory Sections Access Protection
12.12 I/O Memory
13 Peripherals and Architecture
13.1 Peripheral Address Map
13.2 Interrupt Vector Mapping
13.3 SYSCFG - System Configuration
14 Getting Started with Software Development
15 GPR - General Purpose Registers
15.1 Register Summary
15.2 Register Description
16 NVMCTRL - Nonvolatile Memory Controller
16.1 Features
16.2 Overview
16.3 Functional Description
16.4 Functional Safety
16.5 Register Summary
16.6 Register Description
17 RAMCTRL - RAM Controller
17.1 Features
17.2 Overview
17.3 Block Diagram
17.4 Functional Description
17.5 Register Summary
17.6 Register Description
18 CLKCTRL - Clock Controller
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary
18.5 Register Description
19 SLPCTRL - Sleep Controller
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Functional Safety
19.5 Register Summary
19.6 Register Description
20 RSTCTRL - Reset Controller
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary
20.5 Register Description
21 CPUINT - CPU Interrupt Controller
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary
21.5 Register Description
22 ERRCTRL - Error Controller
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary
22.5 Register Description
23 EVSYS - Event System
23.1 Features
23.2 Overview
23.3 Functional Description
23.4 Register Summary
23.5 Register Description
24 PORTMUX - Port Multiplexer
24.1 Overview
24.2 Register Summary
24.3 Register Description
25 PORT - I/O Pin Configuration
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary - PORTx
25.5 Register Description - PORTx
25.6 Register Summary - VPORTx
25.7 Register Description - VPORTx
26 MVIO - Multi-Voltage I/O
26.1 Features
26.2 Overview
26.3 Functional Description
26.4 Register Summary
26.5 Register Description
27 BOD - Brown-out Detector
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary
27.5 Register Description
28 VREF - Voltage Reference
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 WDT - Watchdog Timer
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary
29.5 Register Description
30 SWDT - Synchronous Watchdog Timer
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary
30.5 Register Description
31 TCA - 16-bit Timer/Counter Type A
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary - Normal Mode
31.5 Register Description - Normal Mode
31.6 Register Summary - Split Mode
31.7 Register Description - Split Mode
32 TCB - 16-Bit Timer/Counter Type B
32.1 Features
32.2 Overview
32.3 Functional Description
32.4 Register Summary
32.5 Register Description
33 TCD - 12-Bit Timer/Counter Type D
33.1 Features
33.2 Overview
33.3 Functional Description
33.4 Register Summary
33.5 Register Description
34 RTC - Real-Time Counter
34.1 Features
34.2 Overview
34.3 Clocks
34.4 RTC Functional Description
34.5 PIT Functional Description
34.6 Events
34.7 Interrupts
34.8 Sleep Mode Operation
34.9 Synchronization
34.10 Debug Operation
34.11 Register Summary
34.12 Register Description
35 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
35.1 Features
35.2 Overview
35.3 Functional Description
35.4 Register Summary
35.5 Register Description
36 SPI - Serial Peripheral Interface
36.1 Features
36.2 Overview
36.3 Functional Description
36.4 Register Summary
36.5 Register Description
37 TWI - Two-Wire Interface
37.1 Features
37.2 Overview
37.3 Functional Description
37.4 Register Summary
37.5 Register Description
38 CRCSCAN - Cyclic Redundancy Check Memory Scan
38.1 Features
38.2 Overview
38.3 Functional Description
38.4 Functional Safety
38.5 Register Summary
38.6 Register Description
39 CCL - Configurable Custom Logic
39.1 Features
39.2 Overview
39.3 Functional Description
39.4 Register Summary
39.5 Register Description
40 AC - Analog Comparator
40.1 Features
40.2 Overview
40.3 Functional Description
40.4 Register Summary
40.5 Register Description
41 ADC - Analog-to-Digital Converter
41.1 Features
41.2 Overview
41.3 Functional Description
41.4 Register Summary
41.5 Register Description
42 DAC - Digital-to-Analog Converter
42.1 Features
42.2 Overview
42.3 Functional Description
42.4 Register Summary
42.5 Register Description
43 ZCD - Zero-Cross Detector
43.1 Features
43.2 Overview
43.3 Functional Description
43.4 Register Summary
43.5 Register Description
44 UPDI - Unified Program and Debug Interface
44.1 Features
44.2 Overview
44.3 Functional Description
44.4 Register Summary
44.5 Register Description
45 Instruction Set Summary
46 Electrical Characteristics
46.1 Disclaimer
46.2 Absolute Maximum Ratings
46.3 Standard Operating Conditions
46.4 Supply Voltage
46.5 Power Consumption
46.6 Peripherals Power Consumption
46.7 I/O Pins
46.8 Memory Programming Specifications
46.9 Thermal Characteristics
46.10 CLKCTRL
46.11 Voltage Regulator Monitor
46.12 RSTCTRL
46.13 VREF
46.14 TCD
46.15 USART
46.16 SPI
46.17 TWI
46.18 AC
46.19 ADC
46.20 DAC
46.21 ZCD
46.22 UPDI
47 Characteristics Graphs
48 Ordering Information
49 Package Drawings
49.1 Online Package Drawings
49.2 Package Marking Information
49.3 20-Pin SSOP
49.4 28-Pin SSOP
49.5 28-Pin SPDIP
49.6 28-Pin VQFN Wettable Flanks
49.7 32-Pin VQFN Wettable Flanks
49.8 32-Pin TQFP
50 Data Sheet Revision History
50.1 Revision History
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature