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AVR Microcontroller with Core Independent Peripherals and PicoPower technology ATmega48PB/88PB/168PB
Introduction
Features
1 Description
2 Configuration Summary
3 Ordering Information
3.1 ATmega48PB
3.2 ATmega88PB
3.3 ATmega168PB
4 Block Diagram
5 Pin Configurations
5.1 Pin Descriptions
6 I/O Multiplexing
7 Comparison Between Processors
8 Resources
9 Data Retention
10 About Code Examples
11 Capacitive Touch Sensing
11.1 QTouch Library
12 AVR CPU Core
12.1 Overview
12.2 ALU – Arithmetic Logic Unit
12.3 Status Register
12.4 General Purpose Register File
12.5 Stack Pointer
12.6 Instruction Execution Timing
12.7 Reset and Interrupt Handling
13 AVR Memories
13.1 Overview
13.2 In-System Reprogrammable Flash Program Memory
13.3 SRAM Data Memory
13.4 EEPROM Data Memory
13.5 I/O Memory
13.6 Register Description
14 System Clock and Clock Options
14.1 Clock Systems and Their Distribution
14.2 Clock Sources
14.3 Low Power Crystal Oscillator
14.4 Low Frequency Crystal Oscillator
14.5 Calibrated Internal RC Oscillator
14.6 128kHz Internal Oscillator
14.7 External Clock
14.8 Clock Output Buffer
14.9 Timer/Counter Oscillator
14.10 System Clock Prescaler
14.11 Register Description
15 PM - Power Management and Sleep Modes
15.1 Sleep Modes
15.2 BOD Disable
15.3 Idle Mode
15.4 ADC Noise Reduction Mode
15.5 Power-Down Mode
15.6 Power-Save Mode
15.7 Standby Mode
15.8 Extended Standby Mode
15.9 Power Reduction Register
15.10 Minimizing Power Consumption
15.11 Register Description
16 SCRST - System Control and Reset
16.1 Resetting the AVR
16.2 Reset Sources
16.3 Power-on Reset
16.4 External Reset
16.5 Brown-out Detection
16.6 Watchdog System Reset
16.7 Internal Voltage Reference
16.8 Watchdog Timer
16.9 Register Description
17 Interrupts
17.1 Interrupt Vectors in ATmega48PB
17.2 Interrupt Vectors in ATmega88PB
17.3 Interrupt Vectors in ATmega168PB
17.4 Register Description
18 EXINT - External Interrupts
18.1 Pin Change Interrupt Timing
18.2 Register Description
19 I/O-Ports
19.1 Overview
19.2 Ports as General Digital I/O
19.3 Alternate Port Functions
19.4 Register Description
20 TC0 - 8-bit Timer/Counter0 with PWM
20.1 Features
20.2 Overview
20.3 Timer/Counter Clock Sources
20.4 Counter Unit
20.5 Output Compare Unit
20.6 Compare Match Output Unit
20.7 Modes of Operation
20.8 Timer/Counter Timing Diagrams
20.9 Register Description
21 TC1 - 16-bit Timer/Counter1 with PWM
21.1 Features
21.2 Overview
21.3 Accessing 16-bit Timer/Counter Registers
21.4 Timer/Counter Clock Sources
21.5 Counter Unit
21.6 Input Capture Unit
21.7 Output Compare Units
21.8 Compare Match Output Unit
21.9 Modes of Operation
21.10 Timer/Counter Timing Diagrams
21.11 Register Description
22 Timer/Counter 0, 1 Prescalers
22.1 Internal Clock Source
22.2 Prescaler Reset
22.3 External Clock Source
22.4 Register Description
23 TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation
23.1 Features
23.2 Overview
23.3 Timer/Counter Clock Sources
23.4 Counter Unit
23.5 Output Compare Unit
23.6 Compare Match Output Unit
23.7 Modes of Operation
23.8 Timer/Counter Timing Diagrams
23.9 Asynchronous Operation of Timer/Counter2
23.10 Timer/Counter Prescaler
23.11 Register Description
24 SPI – Serial Peripheral Interface
24.1 Features
24.2 Overview
24.3 SS Pin Functionality
24.4 Data Modes
24.5 Register Description
25 USART - Universal Synchronous Asynchronous Receiver Transceiver
25.1 Features
25.2 Overview
25.3 Clock Generation
25.4 Frame Formats
25.5 USART Initialization
25.6 Data Transmission – The USART Transmitter
25.7 Data Reception – The USART Receiver
25.8 Asynchronous Data Reception
25.9 Multi-Processor Communication Mode
25.10 Examples of Baud Rate Setting
25.11 Register Description
26 USARTSPI - USART in SPI Mode
26.1 Features
26.2 Overview
26.3 Clock Generation
26.4 SPI Data Modes and Timing
26.5 Frame Formats
26.6 Data Transfer
26.7 AVR USART MSPIM vs. AVR SPI
26.8 Register Description
27 TWI - 2-wire Serial Interface
27.1 Features
27.2 Two-Wire Serial Interface Bus Definition
27.3 Data Transfer and Frame Format
27.4 Multi-master Bus Systems, Arbitration, and Synchronization
27.5 Overview of the TWI Module
27.6 Using the TWI
27.7 Transmission Modes
27.8 Multi-master Systems and Arbitration
27.9 Register Description
28 AC - Analog Comparator
28.1 Overview
28.2 Analog Comparator Multiplexed Input
28.3 Register Description
29 ADC - Analog to Digital Converter
29.1 Features
29.2 Overview
29.3 Starting a Conversion
29.4 Prescaling and Conversion Timing
29.5 Changing Channel or Reference Selection
29.6 ADC Noise Canceler
29.7 ADC Conversion Result
29.8 Temperature Measurement
29.9 Register Description
30 DBG - debugWIRE On-chip Debug System
30.1 Features
30.2 Overview
30.3 Physical Interface
30.4 Software Break Points
30.5 Limitations of debugWIRE
30.6 Register Description
31 Self-Programming the Flash
31.1 Overview
31.2 Addressing the Flash During Self-Programming
31.3 Register Description
32 BTLDR - Boot Loader Support – Read-While-Write Self-Programming
32.1 Features
32.2 Overview
32.3 Application and Boot Loader Flash Sections
32.4 Read-While-Write and No Read-While-Write Flash Sections
32.5 Boot Loader Lock Bits
32.6 Entering the Boot Loader Program
32.7 Addressing the Flash During Self-Programming
32.8 Self-Programming the Flash
32.9 Register Description
33 MEMPROG- Memory Programming
33.1 Program And Data Memory Lock Bits
33.2 Fuse Bits
33.3 Signature Bytes
33.4 Calibration Byte
33.5 Page Size
33.6 Parallel Programming Parameters, Pin Mapping, and Commands
33.7 Parallel Programming
33.8 Serial Downloading
34 Electrical Characteristics
34.1 Absolute Maximum Ratings
34.2 DC Characteristics
34.3 Speed Grades
34.4 Clock Characteristics
34.5 System and Reset Characteristics
34.6 SPI Timing Characteristics
34.7 Two-wire Serial Interface Characteristics
34.8 ADC Characteristics
34.9 Parallel Programming Characteristics
35 Typical Characteristics
35.1 ATmega48PB/88PB Typical Characteristics
35.2 ATmega168PB Typical Characteristics
36 Register Summary
37 Instruction Set Summary
38 Packaging Information
38.1 32-pin 32A
38.2 32-pin 32MS1
39 Errata
39.1 Errata ATmega48PB
39.2 Errata ATmega88PB
39.3 Errata ATmega168PB
40 Datasheet Revision History
40.1 Rev. DS40001909A – 05/2017
40.2 Rev. 42176G – 03/2016
40.3 Rev. 42176F – 02/2016
40.4 Rev. 42176E – 10/2015
40.5 Rev. 42176D – 04/2015
40.6 Rev. 42176C – 03/2015
40.7 Rev. 42176B – 11/2014
40.8 Rev. 42176A - 11/2014
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