18.4.3 DDR3PHY PHY General Status Register
Name: | DDR3PHY_PGSR |
Offset: | 0x0C |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | RVEIRR | RVERR | |
Access | | | | | | | R | R | |
Reset | | | | | | | 0 | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFTERR | DTIERR | DTERR | DTDONE | DIDONE | ZCDONE | DLDONE | IDONE | |
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 9 – RVEIRR Read Valid Training Intermittent Error
If set, indicates that there was
an intermittent error during read valid training, such as a pass followed by a fail
then followed by another pass.
Bit 8 – RVERR Read Valid Training Error
If set, indicates that a valid read valid placement could not be found during read valid training.
Bit 7 – DFTERR DDR_DQS Drift
Error
If set, indicates that at least
one of the read data strobes has drifted by more than or equal to the drift limit
set in DDR3PHY_PGCR.
Bit 6 – DTIERR DDR_DQS Gate Training
Intermittent Error
If set, indicates that there was
an intermittent error during DDR_DQS gate
training, such as a pass followed by a fail then
followed by another pass.
Bit 5 – DTERR DDR_DQS GateTraining
Error
If set, indicates that a valid
DDR_DQS gating window could not be found during
DDR_DQS gate training.
Bit 4 – DTDONE Data Training Done
If set, indicates that the PHY
has finished doing data training.
Bit 3 – DIDONE DRAM Initialization Done
If set, indicates that DRAM
initialization has completed.
Bit 2 – ZCDONE Impedance Calibration Done
If set, indicates that impedance
calibration has completed.
Bit 1 – DLDONE DLL Lock Done
If set, indicates that DLL
locking has completed.
Bit 0 – IDONE Initialization Done
If set, indicates that the DDR
system initialization has completed. This bit is set after all the selected
initialization routines in DDR3PHY_PIR have completed.