SPI Timing Description

Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode.

In asynchronous mode, the maximum SCLK frequency fasync is limited to 7.5MHz. The signal at pin 17 (CLKM) is not required to derive SCLK and may be disabled to reduced power consumption and spurious emissions.

The figures below illustrate the SPI timing and introduces its parameters. The corresponding timing parameter definitions t1 – t9 are defined in the Digital Interface Timing Characteristics.

Figure . SPI Timing, Global Map and Definition of Timing Parameters t5, t6, t8, t9.
Figure . SPI Timing, Detailed Drawing of Timing Parameters t1 to t4.

The SPI is based on a byte-oriented protocol and is always a bidirectional communication between the master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave, it must also transmit one byte to the slave. All bytes are transferred with the MSB first. An SPI transaction is finished by releasing /SEL = H.

An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes.

/SEL = L enables the MISO output driver of the AT86RF212B. The MSB of MISO is valid after t1 and is updated on each SCLK falling edge. If the driver is disabled, there is no internal pull-up transistor connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor.

Note: When both /SEL and /RST are active, the MISO output driver is also enabled.

Referring to the figures above, AT86RF212B MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t3 and t4.

This SPI operational mode is commonly known as “SPI mode 0”.