41.8.7 Driver Control
Name: | DRVCTRL |
Offset: | 0x18 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Enable-Protected |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
FILTERVAL1[3:0] | FILTERVAL0[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
INVEN7 | INVEN6 | INVEN5 | INVEN4 | INVEN3 | INVEN2 | INVEN1 | INVEN0 | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NRV7 | NRV6 | NRV5 | NRV4 | NRV3 | NRV2 | NRV1 | NRV0 | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NRE7 | NRE6 | NRE5 | NRE4 | NRE3 | NRE2 | NRE1 | NRE0 | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:28 – FILTERVAL1[3:0] Non-Recoverable Fault Input 1 Filter Value
These bits define the filter value applied on TCE1 event input line. When the TCE1 event input line is configured as a synchronous event, this value must be 0x0.
Bits 27:24 – FILTERVAL0[3:0] Non-Recoverable Fault Input 0 Filter Value
Bits 16, 17, 18, 19, 20, 21, 22, 23 – INVENx Waveform Output x Inversion
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
Bits 8, 9, 10, 11, 12, 13, 14, 15 – NRVx NRVx Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – NREx Non-Recoverable State x Output Enable
These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition.
Value | Description |
---|---|
0 | Non-recoverable fault tri-state the output. |
1 | Non-recoverable faults set the output to NRVx level. |