Set CTRLB.NEWMSG for the new set of plain text processing.
Load CIPLEN reg.
Load (J0+1) in INTVECT register.
As described in NIST documentation J 0
= IV || 0 31 || 1 when len(IV)=96 and J0 =GHASHH (IV || 0 s+64 || [len(IV)] 64 ) (s is the minimum
number of zeroes that must be padded with the Initialization Vector to make it a
multiple of 128) if len(IV) != 96.
Load plain text in INDATA
register.
Set CTRLB.START as 1.
Wait for INTFLAG.ENCCMP to be set.
AES Hardware generates output in INDATA
register.
Intermediate GHASH is stored in GHASH
register and Cipher Text available in INDATA register.
Continue 3 to 6 till the input of plain text to get the cipher text and the Hash keys.
At the last input, set CTRLB.EOM.
Write last in-data to INDATA reg.
Set CTRLB.START as 1.
Wait for INTFLAG.ENCCMP to be set.
AES Hardware generates output in INDATA
register and final Hash key in GHASH register.
Load [LEN(A)]64||[LEN(C)]64 in INDATA
register and set CTRLB.GFMUL and CTRLB.START as 1.
Wait for INTFLAG.GFMCMP to be set.
AES Hardware generates final GHASH
value in GHASH register.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
