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TUxyHLT Hardware Limit Timer Control
Register
Bit 7 6 5 4 3 2 1 0 EPOL CSYNC START[1:0] RESET[1:0] STOP[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 0 0 0 0 0 0
Bit 7 – EPOL
Reset States: POR/BOR = 0 All Other Resets = u
Bit 6 – CSYNC
Reset States: POR/BOR = 1 All Other Resets = u
Bits 5:4 – START[1:0]
Reset States: POR/BOR = 00 All Other Resets = uu
Bits 3:2 – RESET[1:0]
Reset States: POR/BOR = 00 All Other Resets = uu
Bits 1:0 – STOP[1:0]
Reset States: POR/BOR = 00 All Other Resets = uu
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