TUxyCLK
| Name: | TU8yCLK |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLK[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 4:0 – CLK[4:0]
| Reset States: |
|
| Name: | TU8yCLK |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLK[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Reset States: |
|
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.