All 8-bit PIC devices have a Harvard architecture, which has a separate data memory (RAM) and program memory space. Some devices also implement EEPROM.
The data memory (referred to in the data sheets as the general purpose register file) is banked to reduce the assembly instruction width. A bank is “selected” by one or more instructions that sets one or more bits in an SFR. Consult your device data sheet for the exact operation of the device you are using.
Both the general purpose RAM and SFRs both share the same data space and can appear in all available memory banks. PIC18 devices have all SFRs in the one data bank, but Mid-range and Baseline devices have SFRs at the lower addresses of each bank. Due to the location of SFRs in these devices, the general purpose memory becomes fragmented and this limits the size of most C objects.
The Enhanced Mid-range devices overcome this fragmentation by allowing a linear addressing mode, which allows the general purpose memory to be accessed as one contiguous chunk. Thus, when compiling for these devices, the maximum allowable size of objects typically increases. Objects defined when using PIC18 devices can also typically use the entire data memory.
Many devices have several bytes which can be accessed regardless of which bank is currently selected. This memory is called common memory. The PIC18 data sheets refer to the bank in which this memory is stored as the access bank, and hence it is often referred to as the access bank memory. Since no code is required to select a bank before accessing these locations, access to objects in this memory is typically faster and produces smaller code. The compiler always tries to use this memory if possible.
The program memory space is primarily for executable code, but data can also be located here. There are several ways the different device families locate and read data from this memory, but all objects located here will be read-only.