Contents

Introduction Features 3. Configuration Summary 4. Block Diagram 5. Signal Description 6. Microchip Recommended Power Management Solutions 6.1. MCP16502 PMIC 6.2. MCP16501 PMIC 7. Safety and Security Features 7.1. Design for Safety and IEC60730 Class B Certification 7.1.1. Background Information 7.2. Design for Security 7.3. Safety and IEC 60730 Features 7.4. Security Features 8. Event System 8.1. Real-Time Event List 8.2. Real-Time Event Mapping 9. Package and Pinout 9.1. Package 9.2. Pinout 9.2.1. BGA343 Pinout 10. System Interconnect and Security (SIS) 10.1. System Bus and Interconnect 10.1.1. Block Diagram 10.1.2. AXI Subsystem 10.1.3. AHB Subsystem 10.2. System Interconnect Overview 10.3. Quality of Service (QoS) Overview 10.3.1. Cortex-A7 CPU 10.3.2. DMA 10.3.2.1. DMA Per Queue Outstanding Capabilities 10.3.2.2. DMA Per Queue Outstanding Capabilities 10.3.3. GMAC 10.3.3.1. GMAC Outstanding Capabilities 10.3.3.2. GMAC QoS 10.3.4. SDMMC 10.3.5. ISC 10.3.6. AHB 10.3.7. UDDRC 10.4. TrustZone Security Management 10.4.1. TrustZone System Overview 10.4.1.1. Hardware 10.4.1.2. Software 10.4.1.3. Debug 10.4.2. Core Security Extensions Overview 10.4.3. TrustZone Peripheral Manager (TZPM) 10.4.3.1. Function 10.4.3.2. Example 10.4.3.3. Exceptions 10.4.3.4. Bus Hosts 10.4.3.5. Register Summary 10.4.3.5.1. TZPM_KEY 10.4.3.5.2. TZPM_PIDR0 10.4.3.5.3. TZPM_PIDR1 10.4.3.5.4. TZPM_PIDR2 10.4.3.5.5. TZPM_PIDR3 10.4.4. AHB Matrix (MATRIX) 10.4.4.1. Function 10.4.4.2. Programming 10.4.5. TrustZone Address Space Controller (TZC400) 10.4.5.1. Function 10.4.5.2. Filters 10.4.6. Programmable IO Controller (PIOC) 10.4.7. TrustZone AES Bridge Address Space Controller (TZAESBASC) 10.4.7.1. Function 10.4.7.2. Encryption Behavior 10.4.7.3. Access Denials 10.4.7.4. NAND Flash 10.4.8. TrustZone Watchdog 10.4.8.1. Function 10.4.8.2. Basic Programming Guidelines 10.4.9. Security Module (SECUMOD) 10.4.10. Extended DMA Controller (XDMAC) 10.5. Peripheral Clocks and Security 11. Cortex-A7 Processor (Arm) 11.1. Description 11.1.1. Reference Documents 11.2. Embedded Characteristics 11.3. Clocks 11.4. Power Supplies 11.5. Generic Interrupt Controller (GIC) 11.6. Media Processing Engine (MPE) with NEON Technology 11.7. Debug 11.8. Performance Monitoring Unit (PMU) 11.9. Timestamp Generator 12. External Interrupt Controller (EIC) 12.1. Description 12.2. Embedded Characteristics 12.3. Block Diagram 12.4. I/O Lines Description 12.5. Product Dependencies 12.5.1. I/O Lines 12.5.2. Power Management 12.5.3. External Interrupt Sources 12.6. Functional Description 12.6.1. Interrupt Line Characteristics 12.6.2. External Interrupt Line Programming 12.6.3. Register Write Protection 12.7. Register Summary 12.7.1. EIC Glitch Filter Configuration Status Register 12.7.2. EIC Source Configuration Register x 12.7.3. EIC Write Protection Mode Register 12.7.4. EIC Write Protection Status Register 13. Debug and Test 13.1. Description 13.1.1. Reference Documents 13.2. Embedded Characteristics 13.3. Block Diagram 13.4. Pin Description 13.5. Functional Description 13.5.1. Test Pin 13.5.2. EmbeddedICE™ 13.5.3. JTAG Signal Description 13.5.4. Chip Access Using JTAG Connection 13.5.5. IEEE 1149.1 JTAG Boundary Scan 13.5.6. JTAG ID Code Register 13.5.7. Cortex-A7 DP Identification Code Register IDCODE 13.5.7.1. JTAG Debug Port (JTAG-DP) 13.5.7.2. Serial Wire Debug Port (SW-DP) 13.5.8. Debug ROM 14. NIC-400 Global Programmer’s View (NICGPV) 14.1. Description 14.2. Register Summary 14.2.1. AMIB Bus Matrix Issuing Functionality Modification Register 14.2.2. ASIB Read Channel QoS Register 14.2.3. ASIB Write Channel QoS Register 14.2.4. ASIB QoS Control Register 14.2.5. ASIB Maximum Number of Outstanding Transactions Register 14.2.6. ASIB Maximum Combined Outstanding Transactions Register 14.2.7. ASIB Write Address Channel Peak Rate Register 14.2.8. ASIB Write Address Channel Burstiness Allowance Register 14.2.9. ASIB Write Address Channel Average Rate Register 14.2.10. ASIB Read Address Channel Peak Rate Register 14.2.11. ASIB Read Address Channel Burstiness Allowance Register 14.2.12. ASIB Read Address Channel Average Rate Register 14.2.13. ASIB Feedback Controlled Target Register 14.2.14. ASIB Feedback Controlled Scale Register 14.2.15. ASIB QoS Range Register 14.2.16. IB Bus Matrix Issuing Functionality Modification Register 14.2.17. IB Clock Boundary Synchronization Scheme Register 14.2.18. IB Bypass Merge Register 14.2.19. IB Long Burst Functionality Modification Register 14.2.20. IB Tidemark Register 14.2.21. IB Issuing Functionality Modification Register 15. Bus Matrix (MATRIX) 15.1. Description 15.2. Embedded Characteristics 15.3. Memory Mapping 15.4. Special Bus Granting Techniques 15.5. No Default Host 15.6. Last Access Host 15.7. Fixed Default Host 15.8. Arbitration 15.8.1. Arbitration Scheduling 15.8.1.1. Undefined Length Burst Arbitration 15.8.1.2. Slot Cycle Limit Arbitration 15.8.2. Arbitration Priority Scheme 15.8.2.1. Fixed Priority Arbitration 15.8.2.2. Round-Robin Arbitration 15.9. Register Write Protection 15.10. TrustZone Extension 15.10.1. Security Types of System Bus Clients 15.10.1.1. Principles 15.10.1.2. Examples 15.10.2. Security Types of System Bus Hosts 15.10.3. Security of Peripheral Bus Clients 15.11. Register Summary 15.11.1. MATRIX Host Configuration Register x 15.11.2. MATRIX Client Configuration Register x 15.11.3. MATRIX Priority Register A For Clients x 15.11.4. MATRIX Priority Register B For Clients x 15.11.5. MATRIX Host Remap Control Register 15.11.6. MATRIX Host Error Interrupt Enable Register 15.11.7. MATRIX Host Error Interrupt Disable Register 15.11.8. MATRIX Host Error Interrupt Mask Register 15.11.9. MATRIX Host Error Status Register 15.11.10. MATRIX Host Error Address Register x 15.11.11. MATRIX Write Protection Mode Register 15.11.12. MATRIX Write Protection Status Register 15.11.13. MATRIX Security Client Register x 15.11.14. MATRIX Security Areas Split Client Register x 15.11.15. MATRIX Security Region Top Client Register x 15.11.16. MATRIX Security Peripheral Select x Register [x=1..3] 16. DMA Controller (XDMAC) 16.1. Description 16.2. Embedded Characteristics 16.3. Block Diagram 16.4. DMA Controller Peripheral Connections 16.5. Functional Description 16.5.1. Basic Definitions 16.5.2. Data Striding Diagram 16.5.3. Transfer Hierarchy Diagrams 16.5.4. Peripheral Synchronized Transfer 16.5.4.1. Peripheral to Memory Transfer 16.5.4.2. Memory to Peripheral Transfer 16.5.4.3. Software Triggered Synchronized Transfer 16.5.5. XDMAC Transfer Software Operation 16.5.5.1. Single Block Transfer With Single Microblock 16.5.5.2. Single Block Transfer With Multiple Microblock 16.5.5.3. Host Transfer 16.5.5.4. Disabling A Channel Before Transfer Completion 16.6. Linked List Descriptor Operation 16.6.1. Linked List Descriptor View 16.6.1.1. Channel Next Descriptor View 0–3 Structures 16.6.2. Descriptor Structure Members Description 16.6.2.1. MBR_UBC 16.7. XDMAC Maintenance Software Operations 16.7.1. Disabling a Channel 16.7.2. Suspending a Channel 16.7.3. Flushing a Channel 16.7.4. Maintenance Operation Priority 16.7.4.1. Disable Operation Priority 16.7.4.2. Flush Operation Priority 16.7.4.3. Suspend Operation Priority 16.8. XDMAC Software Requirements 16.9. Register Summary 16.9.1. XDMAC_GTYPE 16.9.2. XDMAC Global Configuration Register 16.9.3. XDMAC Global Weighted Arbiter Configuration Register 16.9.4. XDMAC Global Interrupt Enable Register 16.9.5. XDMAC Global Interrupt Disable Register 16.9.6. XDMAC Global Interrupt Mask Register 16.9.7. XDMAC Global Interrupt Status Register 16.9.8. XDMAC Global Channel Enable Register 16.9.9. XDMAC Global Channel Disable Register 16.9.10. XDMAC Global Channel Status Register 16.9.11. XDMAC Global Channel Read Suspend Register 16.9.12. XDMAC Global Channel Write Suspend Register 16.9.13. XDMAC Global Channel Read Write Suspend Register 16.9.14. XDMAC Global Channel Read Write Resume Register 16.9.15. XDMAC Global Channel Read Suspend Status Register 16.9.16. XDMAC Global Channel Write Suspend Status Register 16.9.17. XDMAC Global Channel Read Resume Register 16.9.18. XDMAC Global Channel Write Resume Register 16.9.19. XDMAC Global Channel Software Request Register 16.9.20. XDMAC Global Channel Software Request Status Register 16.9.21. XDMAC Global Channel Software Flush Request Register 16.9.22. XDMAC Channel x Interrupt Enable Register [x=0..31] 16.9.23. XDMAC Channel x Interrupt Disable Register [x = 0..31] 16.9.24. XDMAC Channel x Interrupt Mask Register [x = 0..31] 16.9.25. XDMAC Channel x Interrupt Status Register [x = 0..31] 16.9.26. XDMAC Channel x Source Address Register [x = 0..31] 16.9.27. XDMAC Channel x Destination Address Register [x = 0..31] 16.9.28. XDMAC Channel x Next Descriptor Address Register [x = 0..31] 16.9.29. XDMAC Channel x Next Descriptor Control Register [x = 0..31] 16.9.30. XDMAC Channel x Microblock Control Register [x = 0..31] 16.9.31. XDMAC Channel x Block Control Register [x = 0..31] 16.9.32. XDMAC Channel x Configuration Register [x = 0..31] 16.9.33. XDMAC Channel x Data Stride Memory Set Pattern Register [x = 0..31] 16.9.34. XDMAC Channel x Source Microblock Stride Register [x = 0..31] 16.9.35. XDMAC Channel x Destination Microblock Stride Register [x = 0..31] 16.9.36. XDMAC Channel x Transfer Count Status Register [x = 0..XDMAC_NB_CH-131] 17. MEMORIES 17.1. Embedded Memories 17.1.1. Internal SRAM 17.1.2. Internal ROM 17.2. External Memories 17.2.1. Universal DDR-SDRAM Controller (UDDRC) 17.2.2. External Bus Interface (EBI) 17.2.2.1. Description 17.3. Product Dependencies 17.3.1. Clocks 17.3.2. Interrupts 17.3.3. Reset 17.3.4. I/Os 17.4. Special Functions in SFR/SFRBU 18. Static Memory Controller (SMC) 18.1. Description 18.2. Embedded Characteristics 18.3. Block Diagram 18.4. I/O Lines Description 18.5. Multiplexed Signals 18.6. Application Example 18.6.1. Hardware Interface 18.7. Product Dependencies 18.7.1. I/O Lines 18.7.2. Power Management 18.7.3. Interrupt Sources 18.8. External Memory Mapping 18.9. Connection to External Devices 18.9.1. Data Bus Width 18.9.2. Byte Write or Byte Select Access 18.9.2.1. Byte Write Access 18.9.2.2. Byte Select Access 18.9.2.3. Signal Multiplexing 18.10. Standard Read and Write Protocols 18.10.1. Read Waveforms 18.10.1.1. NRD Waveform 18.10.1.2. NCS Waveform 18.10.1.3. Read Cycle 18.10.2. Read Mode 18.10.2.1. Read is Controlled by NRD (READ_MODE = 1) 18.10.2.2. Read is Controlled by NCS (READ_MODE = 0) 18.10.3. Write Waveforms 18.10.3.1. NWE Waveforms 18.10.3.2. NCS Waveforms 18.10.3.3. Write Cycle 18.10.4. Write Mode 18.10.4.1. Write is Controlled by NWE (WRITE_MODE = 1) 18.10.4.2. Write is Controlled by NCS (WRITE_MODE = 0) 18.10.5. External Bus Clock 18.10.6. Coding Timing Parameters 18.10.7. Reset Values of Timing Parameters 18.10.8. Usage Restriction 18.10.8.1. For Read Operations 18.10.8.2. For Write Operations 18.10.8.3. For Read and Write Operations 18.11. Scrambling/Unscrambling Function 18.12. Automatic Wait States 18.12.1. Chip Select Wait States 18.12.2. Early Read Wait State 18.12.3. Reload User Configuration Wait State 18.12.3.1. User Procedure 18.12.3.2. Slow Clock Mode Transition 18.12.4. Read to Write Wait State 18.13. External Wait 18.13.1. Restriction 18.13.2. Frozen Mode 18.13.3. Ready Mode 18.13.4. NWAIT Latency and Read/Write Timings 18.14. Slow Clock Mode 18.14.1. Slow Clock Mode Waveforms 18.14.2. Switching from (to) Slow Clock Mode to (from) Normal Mode 18.15. Register Write Protection 18.16. NFC Operations 18.16.1. NFC Overview 18.16.2. NFC Control Registers 18.16.2.1. Building NFC Address Command Example 18.16.2.2. NFCADDR_CMD 18.16.2.3. NFCDATA_ADDT 18.16.2.4. NFCDATA_STATUS 18.16.3. NFC Initialization 18.16.3.1. NFC Timing Engine 18.16.4. NFC SRAM 18.16.4.1. NFC SRAM Mapping 18.16.4.2. NFC SRAM Access Prioritization Algorithm 18.16.5. NAND Flash Operations 18.16.5.1. Page Read 18.16.5.2. Program Page 18.17. PMECC Controller Functional Description 18.17.1. MLC/SLC Write Page Operation Using PMECC 18.17.1.1. SLC/MLC Write Operation with Spare Enable Bit Set 18.17.1.2. SLC/MLC Write Operation with Spare Disable 18.17.2. MLC/SLC Read Page Operation Using PMECC 18.17.2.1. MLC/SLC Read Operation with Spare Decoding 18.17.2.2. MLC/SLC Read Operation 18.17.2.3. MLC/SLC User Read ECC Area 18.17.2.4. MLC Controller Working with NFC 18.18. Software Implementation 18.18.1. Remainder Substitution Procedure 18.18.2. Finding the Error Location Polynomial Sigma(x) 18.18.3. Finding the Error Position 18.18.3.1. Error Location 18.19. Register Summary 18.19.1. NFC Configuration Register 18.19.2. NFC Control Register 18.19.3. HSMC_SR 18.19.4. NFC Interrupt Enable Register 18.19.5. NFC Interrupt Disable Register 18.19.6. NFC Interrupt Mask Register 18.19.7. NFC Address Cycle Zero Register 18.19.8. NFC Bank Register 18.19.9. PMECC Configuration Register 18.19.10. PMECC Spare Area Size Register 18.19.11. PMECC Start Address Register 18.19.12. PMECC End Address Register 18.19.13. PMECC Control Register 18.19.14. PMECC Status Register 18.19.15. PMECC Interrupt Enable Register 18.19.16. PMECC Interrupt Disable Register 18.19.17. PMECC Interrupt Mask Register 18.19.18. PMECC Interrupt Status Register 18.19.19. PMECC Redundancy x Register 18.19.20. PMECC Remainder x Register 18.19.21. PMECC Error Location Configuration Register 18.19.22. PMECC Error Location Primitive Register 18.19.23. PMECC Error Location Enable Register 18.19.24. PMECC Error Location Disable Register 18.19.25. PMECC Error Location Status Register 18.19.26. PMECC Error Location Interrupt Enable Register 18.19.27. PMECC Error Location Interrupt Disable Register 18.19.28. PMECC Error Location Interrupt Mask Register 18.19.29. PMECC Error Location Interrupt Status Register 18.19.30. PMECC Error Location SIGMA0 Register 18.19.31. PMECC Error Location SIGMAx Register 18.19.32. PMECC Error Location x Register 18.19.33. Setup Register 18.19.34. Pulse Register 18.19.35. Cycle Register 18.19.36. Timings Register 18.19.37. Mode Register 18.19.38. Off Chip Memory Scrambling Register 18.19.39. Off Chip Memory Scrambling Key1 Register 18.19.40. Off Chip Memory Scrambling Key2 Register 18.19.41. HSMC_CLKCFG 18.19.42. Write Protection Mode Register 18.19.43. Write Protection Status Register 19. Universal DDR Memory Controller (UDDRC) 19.1. Description 19.2. Embedded Characteristics 19.3. Block Diagram 19.4. I/O Lines Description 19.4.1. Product Dependencies 19.4.2. Implementation Example 19.5. Functional Description 19.5.1. AXI Port Interface (XPI) 19.5.1.1. Read Address Channel 19.5.1.2. Write Address Channel 19.5.1.3. Wrap Burst Expansion 19.5.1.4. Software Coherency for AXI Ports 19.5.2. Port Arbiter (PA) 19.5.2.1. Registers Related to Port Arbiter 19.5.3. Address Mapper 19.5.3.1. System Address Regions 19.5.3.2. Application to HIF Address Mapping 19.5.3.3. HIF Address to SDRAM Address Mapping 19.5.3.4. Registers Related to Address Mapper 19.5.4. Address Collision Handling 19.5.5. Quality of Service (QoS) 19.5.5.1. Traffic Classes 19.5.5.1.1. Read Classes 19.5.5.1.2. Write Classes 19.5.5.1.3. QoS Mapping 19.5.5.1.4. Dual Read Address Queue 19.5.5.1.5. ID Collisions 19.5.5.2. VPR/VPW Timeout 19.5.5.3. Registers Related to QoS 19.5.6. Bypass Operation 19.5.6.1. Enabling Bypass Operation 19.5.6.2. Registers Related to Bypass Operation 19.5.7. Burst Mode Operation 19.5.8. Refresh Controls 19.5.8.1. Refresh Using Direct Software Request of Refresh Command 19.5.8.2. Refresh Using Auto Refresh Feature Inside the UDDRC 19.5.8.2.1. Single Refresh 19.5.8.2.2. Burst Refresh 19.5.8.2.3. Speculative Refresh 19.5.8.2.4. Per-bank Refresh (LPDDR2/LPDDR3 only) 19.5.8.2.5. Constraints on refresh_timerX_start_value_x32 19.5.8.2.6. Registers Related to Refresh Controls 19.5.9. ZQ Calibration 19.5.9.1. DDR3 Devices 19.5.9.2. LPDDR2/LPDDR3 Devices 19.5.9.3. Automatic and Software Initiated ZQCS 19.5.9.4. LPDDR2/LPDDR3 ZQ Reset Command 19.5.9.5. Registers Related to ZQ Calibration 19.5.10. ODT Control 19.5.10.1. Registers Related to ODT Control 19.5.11. High-Level SDRAM Initialization Procedure 19.5.11.1. Global Configuration 19.5.11.2. Step 1 19.5.11.3. Step 2 19.5.11.4. Step 3 19.5.11.5. Step 4 19.5.11.6. Step 5 19.5.11.7. Step 6 19.5.11.8. Step 7 19.5.11.9. Step 8 19.5.11.10. Step 9 19.5.11.11. Step 10 19.5.11.12. Step 11 19.5.11.13. Step 12 19.5.11.14. Step 13 19.5.11.15. Step 14 19.5.11.16. Step 15 19.5.11.17. Step 16 19.5.12. Mode Register Reads and Writes 19.5.12.1. Mode Register Write 19.5.12.2. Mode Register Read 19.5.12.3. Registers Related to Mode Register Reads and Writes 19.5.13. 2T Memory Command Timing 19.5.14. Power Saving Features 19.5.14.1. SDRAM Power Saving Features 19.5.14.1.1. Precharge Power-down 19.5.14.1.2. Deep Power-Down 19.5.14.1.3. Assertion of dfi_dram_clk_disable 19.5.14.1.4. DLL-off Mode (DDR3) 19.5.14.2. Power Saving in PHY through DFI Low-Power Interface 19.5.14.3. Software Sequence for Removal of Clocks 19.5.14.4. Power Removal Flow 19.5.14.5. Registers Related to Power-Saving Features 19.6. Register Summary 19.6.1. UDDRC Host Register 0 19.6.2. UDDRC Operating Mode Status Register 19.6.3. UDDRC Mode Register Read/Write Control Register 0 19.6.4. UDDRC Mode Register Read/Write Control Register 1 19.6.5. UDDRC Mode Register Read/Write Status Register 19.6.6. UDDRC Temperature Derate Enable Register 19.6.7. UDDRC Temperature Derate Interval Register 19.6.8. UDDRC Temperature Derate Control Register 19.6.9. UDDRC Low Power Control Register 19.6.10. UDDRC Low Power Timing Register 19.6.11. UDDRC Hardware Low Power Control Register 19.6.12. UDDRC Refresh Control Register 0 19.6.13. UDDRC Refresh Control Register 3 19.6.14. UDDRC Refresh Timing Register 19.6.15. UDDRC CRC Parity Control Register 0 19.6.16. UDDRC CRC Parity Status Register 19.6.17. UDDRC SDRAM Initialization Register 0 19.6.18. UDDRC SDRAM Initialization Register 1 19.6.19. UDDRC SDRAM Initialization Register 2 19.6.20. UDDRC SDRAM Initialization Register 3 19.6.21. UDDRC SDRAM Initialization Register 4 19.6.22. UDDRC SDRAM Initialization Register 5 19.6.23. UDDRC DIMM Control Register 19.6.24. UDDRC SDRAM Timing Register 0 19.6.25. UDDRC SDRAM Timing Register 1 19.6.26. UDDRC SDRAM Timing Register 2 19.6.27. UDDRC SDRAM Timing Register 3 19.6.28. UDDRC SDRAM Timing Register 4 19.6.29. UDDRC SDRAM Timing Register 5 19.6.30. UDDRC SDRAM Timing Register 6 19.6.31. UDDRC SDRAM Timing Register 7 19.6.32. UDDRC SDRAM Timing Register 8 19.6.33. UDDRC SDRAM Timing Register 14 19.6.34. UDDRC SDRAM Timing Register 15 19.6.35. UDDRC ZQ Control Register 0 19.6.36. UDDRC ZQ Control Register 1 19.6.37. UDDRC ZQ Control Register 2 19.6.38. UDDRC ZQ Status Register 19.6.39. UDDRC DFI Timing Register 0 19.6.40. UDDRC DFI Timing Register 1 19.6.41. UDDRC DFI Low Power Configuration Register 0 19.6.42. UDDRC DFI Update Register 0 19.6.43. UDDRC DFI Update Register 1 19.6.44. UDDRC DFI Update Register 2 19.6.45. UDDRC DFI Miscellaneous Control Register 19.6.46. UDDRC DFI Status Register 19.6.47. UDDRC DFI PHY Host 19.6.48. UDDRC Address Map Register 1 19.6.49. UDDRC Address Map Register 2 19.6.50. UDDRC Address Map Register 3 19.6.51. UDDRC Address Map Register 4 19.6.52. UDDRC Address Map Register 5 19.6.53. UDDRC Address Map Register 6 19.6.54. UDDRC Address Map Register 9 19.6.55. UDDRC Address Map Register 10 19.6.56. UDDRC Address Map Register 11 19.6.57. UDDRC ODT Configuration Register 19.6.58. UDDRC ODT/Rank Map Register 19.6.59. UDDRC Scheduler Control Register 0 19.6.60. UDDRC Scheduler Control Register 1 19.6.61. UDDRC High Priority Read CAM Register 1 19.6.62. UDDRC Low Priority Read CAM Register 1 19.6.63. UDDRC Write CAM Register 1 19.6.64. UDDRC Debug Register 0 19.6.65. UDDRC Debug Register 1 19.6.66. UDDRC CAM Debug Register 19.6.67. UDDRC Command Debug Register 19.6.68. UDDRC Status Debug Register 19.6.69. UDDRC Software Register Programming Control Enable 19.6.70. UDDRC Software Register Programming Control Status 19.6.71. UDDRC AXI Poison Configuration Register. Common for all AXI ports 19.6.72. UDDRC AXI Poison Status Register 19.6.73. UDDRC Temperature Derate Status Register 19.6.74. UDDRC Port Status Register 19.6.75. UDDRC Port Common Configuration Register 19.6.76. UDDRC AXI Port 0 Configuration Read Register 19.6.77. UDDRC AXI Port 0 Configuration Write Register 19.6.78. UDDRC AXI Port 0 Control Register 19.6.79. UDDRC AXI Port 0 Read QoS Configuration Register 0 19.6.80. UDDRC AXI Port 0 Read QoS Configuration Register 1 19.6.81. UDDRC AXI Port 0 Write QoS Configuration Register 0 19.6.82. UDDRC AXI Port 0 Write QoS Configuration Register 1 19.6.83. UDDRC AXI Port 1 Configuration Read Register 19.6.84. UDDRC AXI Port 1 Configuration Write Register 19.6.85. UDDRC AXI Port 1 Control Register 19.6.86. UDDRC AXI Port 1 Read QoS Configuration Register 0 19.6.87. UDDRC AXI Port 1 Read QoS Configuration Register 1 19.6.88. UDDRC AXI Port 1 Write QoS Configuration Register 0 19.6.89. UDDRC AXI Port 1 Write QoS Configuration Register 1 19.6.90. UDDRC AXI Port 2 Configuration Read Register 19.6.91. UDDRC AXI Port 2 Configuration Write Register 19.6.92. UDDRC AXI Port 2 Control Register 19.6.93. UDDRC AXI Port 2 Read QoS Configuration Register 0 19.6.94. UDDRC AXI Port 2 Read QoS Configuration Register 1 19.6.95. UDDRC AXI Port 2 Write QoS Configuration Register 0 19.6.96. UDDRC AXI Port 2 Write QoS Configuration Register 1 19.6.97. UDDRC AXI Port 3 Configuration Read Register 19.6.98. UDDRC AXI Port 3 Configuration Write Register 19.6.99. UDDRC AXI Port 3 Control Register 19.6.100. UDDRC AXI Port 3 Read QoS Configuration Register 0 19.6.101. UDDRC AXI Port 3 Read QoS Configuration Register 1 19.6.102. UDDRC AXI Port 3 Write QoS Configuration Register 0 19.6.103. UDDRC AXI Port 3 Write QoS Configuration Register 1 19.6.104. UDDRC AXI Port 4 Configuration Read Register 19.6.105. UDDRC AXI Port 4 Configuration Write Register 19.6.106. UDDRC AXI Port 4 Control Register 19.6.107. UDDRC AXI Port 4 Read QoS Configuration Register 0 19.6.108. UDDRC AXI Port 4 Read QoS Configuration Register 1 19.6.109. UDDRC AXI Port 4 Write QoS Configuration Register 0 19.6.110. UDDRC AXI Port 4 Write QoS Configuration Register 1 19.6.111. UDDRC SAR Base Address Register 0 19.6.112. UDDRC SAR Size Register 0 20. DDR/LPDDR Physical Interface (DDR3PHY) 20.1. Description 20.2. Embedded Characteristics 20.2.1. Supported PHY Data Rates 20.2.2. Applicable Standards 20.3. Functional Description 20.3.1. Byte Lane PHY 20.3.2. Programming Model 20.3.2.1. Initialization 20.3.2.2. SDRAM Initialization 20.3.3. PHY Registers 20.4. Register Summary 20.4.1. DDR3PHY PHY Initialization Register 20.4.2. DDR3PHY PHY General Configuration Register 20.4.3. DDR3PHY PHY General Status Register 20.4.4. DDR3PHY DLL General Control Register 20.4.5. DDR3PHY AC DLL Control Register 20.4.6. DDR3PHY PHY Timing Register 0 20.4.7. DDR3PHY PHY Timing Register 1 20.4.8. DDR3PHY PHY Timing Register 2 20.4.9. DDR3PHY AC I/O Configuration Register 20.4.10. DDR3PHY DATX8 Common Configuration Register 20.4.11. DDR3PHY DDR System General Configuration Register 20.4.12. DDR3PHY DRAM Configuration Register 20.4.13. DDR3PHY DRAM Timing Parameters Register 0 20.4.14. DDR3PHY DRAM Timing Parameter Register 1 20.4.15. DDR3PHY DRAM Timing Parameter Register 2 20.4.16. DDR3PHY Mode Register 0 (MR0) (DDR3 Mode) 20.4.17. DDR3PHY Mode Register 0 (MR0) (DDR2 Mode) 20.4.18. DDR3PHY Mode Register 0 (MR0) (DDR Mode) 20.4.19. DDR3PHY Mode Register 1 (MR1) (DDR3 Mode) 20.4.20. DDR3PHY Mode Register 1 (MR1) (DDR2 Mode) 20.4.21. DDR3PHY Mode Register 1 (MR1) (DDR Mode) 20.4.22. DDR3PHY Mode Register 1 (MR1) (LPDDR2 Mode) 20.4.23. DDR3PHY Mode Register 1 (MR1) (LPDDR3 Mode) 20.4.24. DDR3PHY Mode Register 2 (MR2/EMR2) (DDR3 Mode) 20.4.25. DDR3PHY Mode Register 2 (MR2/EMR2) (DDR2 Mode) 20.4.26. DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR2 Mode) 20.4.27. DDR3PHY Mode Register 2 (MR2/EMR2) (LPDDR3 Mode) 20.4.28. DDR3PHY Mode Register 3 (MR3) (DDR3 Mode) 20.4.29. DDR3PHY Mode Register 3 (MR3) (DDR2 Mode) 20.4.30. DDR3PHY Mode Register 3 (MR3) (LPDDR2 Mode) 20.4.31. DDR3PHY Mode Register 3 (MR3) (LPDDR3 Mode) 20.4.32. DDR3PHY ODT Configuration Register 20.4.33. DDR3PHY Data Training Address Register 20.4.34. DDR3PHY Data Training Data Register 0 20.4.35. DDR3PHY Data Training Data Register 1 20.4.36. DDR3PHY DCU Address Register 20.4.37. DDR3PHY DCU Data Register 20.4.38. DDR3PHY DCU Run Register 20.4.39. DDR3PHY DCU Loop Register 20.4.40. DDR3PHY DCU General Configuration Register 20.4.41. DDR3PHY DCU Timing Parameter Register 20.4.42. DDR3PHY DCU Status Register 0 20.4.43. DDR3PHY DCU Status Register 1 20.4.44. DDR3PHY BIST Run Register 20.4.45. DDR3PHY BIST Word Count Register 20.4.46. DDR3PHY BIST Mask 0 Register 20.4.47. DDR3PHY BIST Mask 1 Register 20.4.48. DDR3PHY BIST LFSR Seed Register 20.4.49. DDR3PHY BIST Address 0 Register 20.4.50. DDR3PHY BIST Address 1 Register 20.4.51. DDR3PHY BIST Address 2 Register 20.4.52. DDR3PHY BIST User Data Pattern Register 20.4.53. DDR3PHY General Status Register 20.4.54. DDR3PHY Word Error Register 20.4.55. DDR3PHY BIST Bit Error 0 Register 20.4.56. DDR3PHY BIST Bit Error 1 Register 20.4.57. DDR3PHY BIST Bit Error 2 Register 20.4.58. DDR3PHY BIST Word Count Status Register 20.4.59. DDR3PHY Fail Word 0 Register 20.4.60. DDR3PHY Fail Word 1 Register 20.4.61. DDR3PHY ZQ Impedance Control Register 0 20.4.62. DDR3PHY ZQ Impedance Control Register 1 20.4.63. DDR3PHY ZQ Status Register 0 20.4.64. DDR3PHY ZQ Status Register 1 20.4.65. DDR3PHY DATX8 General Configuration Register 20.4.66. DDR3PHY DATX8 General Status Register 0 20.4.67. DDR3PHY DATX8 General Status Register 1 20.4.68. DDR3PHY DATX8 DLL Control Register 20.4.69. DDR3PHY DATX8 DQ Timing Register 20.4.70. DDR3PHY DATX8 DQS Timing Register 21. Boot Strategies 21.1. Standard Boot Strategies 21.1.1. Overview 21.1.2. Flow Diagram 21.1.3. Chip Setup 21.1.4. Standard Boot Configuration 21.1.4.1. Default Boot Sequence 21.1.4.2. Boot Configuration Packet 21.1.4.3. BSC_CR 21.1.4.4. Boot Configuration User Interface 21.1.4.5. MON_DIS 21.1.4.6. CONSOLE_PIN 21.1.4.7. MEM_CFGx[0] 21.1.4.8. MEM_CFGx[1] 21.1.4.9. MEM_CFGx[0] 21.1.4.10. MEM_CFGx[1] 21.1.4.11. NVM Boot Sequence 21.1.4.12. Valid Code Detection 21.1.4.12.1. Arm Exception Vector Check 21.1.4.12.2. boot.bin File Check 21.1.4.13. Detailed Memory Boot Procedures 21.1.4.13.1. SD Card/e.MMC Boot 21.1.4.13.2. SPI Flash Boot 21.1.4.13.3. QSPI NOR Flash Boot 21.1.4.14. Hardware and Software Constraints 21.1.5. Standard Monitor 21.1.5.1. Command List 21.1.5.2. DBGU/UART Console Port 21.1.5.2.1. Xmodem Protocol 21.1.5.3. USB Device Port 21.1.5.3.1. Supported External Crystal/External Clocks 21.1.5.3.2. USB Class 21.1.5.3.3. Enumeration Process 21.1.5.3.4. Communication Endpoints 21.2. Secure Boot Strategies 21.2.1. Overview 21.2.2. Flow Diagram 21.2.3. Secure Boot Configuration 21.2.4. Secure Boot Configuration User Interface 21.2.4.1. Secure Boot Mode Enable 21.2.4.2. Authentication Mode 21.2.4.3. Pairing Mode Enable 21.2.4.4. Key Written 21.2.4.5. Initialization Vector Address 21.2.4.6. RSA Public Key Hash Address 21.2.4.7. AES-CBC Key Address 21.2.4.8. AES-CMAC Key Address Register 21.2.5. Secure Valid Code Detection 21.2.5.1. 6th Vector Format 21.2.5.2. e.MMC/SD Card File System 21.2.6. Encryption, Decryption and Authentication 21.2.7. Secure Boot Mode Configuration 21.2.8. Programming a Boot File 21.2.9. Secure Monitor 21.2.9.1. Generic Commands 21.2.9.2. Command Format 21.2.9.3. Monitor Answer 21.2.9.4. Command Description 21.2.9.4.1. Read ROM Code Version 21.2.9.4.2. Write Customer Key 21.2.9.4.3. Programming External Memories 21.3. Key Provisioning and Bootstrap Programming 21.3.1. Configuring Secure Boot Mode 21.3.2. Bootstrap Development and Updates 21.3.2.1. Bootstrap Ciphering 21.3.2.2. Bootstrap Field Update 21.3.2.2.1. Case 1: SAM-BA Monitor is disabled (the “MON_DIS” word is filled in the Boot Configuration Packet) 21.3.2.2.2. Case 2: Secure SAM-BA Monitor is still available (the “MON_DIS” word is zeroed in the Boot Configuration Packet - not recommended for systems in production) 21.3.3. Monitor Disabling by the Bootstrap 22. SYSTEM CONTROLLER SUBSYSTEM 22.1. Block Diagram 22.2. Components 22.3. Product Dependencies 22.3.1. Clocks 22.3.1.1. Changing System Frequencies 22.3.2. Interrupts 22.3.3. Reset 22.3.4. I/Os 22.3.5. Power Supplies 22.4. Special Functions in SFR/SFRBU 23. System Controller Write Protection (SYSCWP) 23.1. Functional Description 23.1.1. System Controller Peripheral Mapping 23.1.2. Register Write Protection 23.2. Register Summary 23.2.1. SYSC Write Protection Mode Register 23.2.2. SYSC Write Protection Status Register 24. General Purpose Backup Registers (GPBR) 24.1. Description 24.2. Embedded Characteristics 24.3. Register Summary 24.3.1. GPBR Mode Register 24.3.2. GPBR_FCLR 24.3.3. General Purpose Backup Register x [x=0..1] 25. Dual Watchdog Timer (DWDT) 25.1. Description 25.2. Embedded Characteristics 25.3. Block Diagram 25.4. Functional Description 25.4.1. Configuration 25.4.2. Watchdog Reload 25.4.3. Watchdog Lock 25.4.4. Repeat Threshold 25.4.5. Watchdog Reset Order 25.4.6. Watchdog Interrupt 25.4.7. Security Module 25.4.8. Watchdog Halt 25.4.9. Timing Diagrams 25.5. Register Summary 25.5.1. NS_WDT_CR 25.5.2. NS_WDT_MR 25.5.3. NS_WDT_VR 25.5.4. NS_WDT_WL 25.5.5. DWDT Never Secure Watchdog Timer Interrupt Level Register 25.5.6. DWDT Never Secure Watchdog Interrupt Enable Register 25.5.7. DWDT Never Secure Watchdog Interrupt Disable Register 25.5.8. DWDT Never Secure Watchdog Interrupt Status Register 25.5.9. DWDT Never Secure Watchdog Interrupt Mask Register 25.5.11. DWDT Programmable Secure Watchdog Timer Control Register 25.5.12. DWDT Programmable Secure Watchdog Timer Mode Register 25.5.13. DWDT Programmable Secure Watchdog Timer Value Register 25.5.14. DWDT Programmable Secure Watchdog Timer Window Level Register 25.5.15. DWDT Programmable Secure Watchdog Timer Interrupt Level Register 25.5.16. DWDT Programmable Secure Watchdog Interrupt Enable Register 25.5.17. DWDT Programmable Secure Watchdog Interrupt Disable Register 25.5.18. DWDT Programmable Secure Watchdog Interrupt Status Register 25.5.19. DWDT Programmable Secure Watchdog Interrupt Mask Register 25.5.20. DWDT Never Secure Level Limit Register 25.5.21. DWDT Never Secure Repeat Threshold Limit Register 25.5.22. DWDT Never Secure Period Limit Register 26. Reset Controller (RSTC) 26.1. Description 26.2. Embedded Characteristics 26.3. Block Diagram 26.4. Functional Description 26.4.1. NRST Manager 26.4.1.1. NRST Signal or Interrupt 26.4.1.2. NRST_OUT External Reset Control 26.4.1.3. USB Reset Control 26.4.1.4. DDR Reset Control 26.4.2. Reset States 26.4.2.1. General Reset 26.4.2.2. Backup Exit Reset 26.4.2.3. 32.768 kHz Crystal Oscillator Failure Detection Reset 26.4.2.4. ULP Mode 2 Reset 26.4.2.5. Watchdog Reset 26.4.2.6. Software Reset 26.4.2.7. User Reset 26.4.3. Reset State Priorities 26.5. Register Summary 26.5.1. RSTC Control Register 26.5.2. RSTC Status Register 26.5.3. RSTC Mode Register 26.5.4. RSTC Generic Reset Register 27. Real-time Timer (RTT) 27.1. Description 27.2. Embedded Characteristics 27.3. Block Diagram 27.4. Functional Description 27.5. Register Summary 27.5.1. Real-time Timer Mode Register 27.5.2. Real-time Timer Alarm Register 27.5.3. Real-time Timer Value Register 27.5.4. Real-time Timer Status Register 27.5.5. Real-time Timer Modulo Selection Register 27.5.6. RTT_TSR 28. Real-time Clock (RTC) 28.1. Description 28.2. Embedded Characteristics 28.3. Block Diagram 28.4. Product Dependencies 28.4.1. Power Management 28.4.2. Interrupt 28.5. Functional Description 28.5.1. Reference Clock 28.5.2. Timing 28.5.3. Alarm 28.5.4. Error Checking when Programming 28.5.5. RTC Internal Free-Running Counter Error Checking 28.5.6. Updating Time/Calendar 28.5.6.1. Gregorian and Persian Modes 28.5.6.2. UTC Mode 28.5.7. RTC Accurate Clock Calibration 28.5.8. Waveform Generation 28.5.9. Tamper Timestamping 28.6. Register Summary 28.6.1. RTC Control Register 28.6.2. RTC Mode Register 28.6.3. RTC Time Register 28.6.4. RTC Time Register (UTC_MODE) 28.6.5. RTC Calendar Register 28.6.6. RTC Time Alarm Register 28.6.7. RTC Time Alarm Register (UTC_MODE) 28.6.8. RTC Calendar Alarm Register 28.6.9. RTC Calendar Alarm Register (UTC_MODE) 28.6.10. RTC Status Register 28.6.11. RTC Status Clear Command Register 28.6.12. RTC Interrupt Enable Register 28.6.13. RTC Interrupt Disable Register 28.6.14. RTC Interrupt Mask Register 28.6.15. RTC Valid Entry Register 28.6.16. RTC TimeStamp Time Register 0 28.6.17. RTC TimeStamp Time Register 0 (UTC_MODE) 28.6.18. RTC TimeStamp Time Register 1 28.6.19. RTC TimeStamp Time Register 1 (UTC_MODE) 28.6.20. RTC TimeStamp Date Register 28.6.21. RTC TimeStamp Date Register (UTC_MODE) 28.6.22. RTC TimeStamp Source Register 29. Shutdown Controller (SHDWC) 29.1. Description 29.2. Embedded Characteristics 29.3. Block Diagram 29.4. I/O Lines Description 29.5. Product Dependencies 29.5.1. Power Management 29.6. Functional Description 29.6.1. Wake-up Inputs 29.6.2. Low-Power Mode Pin Control 29.7. Register Summary 29.7.1. SHDWC Control Register 29.7.2. SHDWC Mode Register 29.7.3. SHDWC Status Register 29.7.4. SHDWC Wake-up Inputs Register 30. 64-bit Periodic Interval Timer (PIT64B) 30.1. Description 30.2. Embedded Characteristics 30.3. Block Diagram 30.4. Product Dependencies 30.4.1. Power Management 30.4.2. Interrupt Generation 30.5. Functional Description 30.5.1. Timer Clock Source 30.5.2. Single Period Mode 30.5.3. Continuous Period Mode 30.5.4. Security and Safety Analysis and Reports 30.5.5. Register Write Protection 30.6. Register Summary 30.6.1. PIT64B Control Register 30.6.2. PIT64B Mode Register 30.6.3. PIT64B LSB Period Register 30.6.4. PIT64B MSB Period Register 30.6.5. PIT64B Interrupt Enable Register 30.6.6. PIT64B Interrupt Disable Register 30.6.7. PIT64B Interrupt Mask Register 30.6.8. PIT64B Interrupt Status Register 30.6.9. PIT64B Timer LSB Register 30.6.10. PIT64B Timer MSB Register 30.6.11. PIT64B Write Protection Mode Register 30.6.12. PIT64B Write Protection Status Register 31. Chip Identifier (CHIPID) 31.1. Description 31.2. Embedded Characteristics 31.3. Register Summary 31.3.1. Chip ID Register 31.3.2. Chip ID Extension Register 32. OTP Memory Controller (OTPC) 32.1. Description 32.2. Embedded Characteristics 32.3. Block Diagram 32.4. Product Dependencies 32.4.1. Power Management 32.4.2. Interrupt Sources 32.5. Functional Description 32.5.1. Bus Interfaces 32.5.2. OTP Memory Partitioning 32.5.3. User Area 32.5.3.1. Area Configuration and Control 32.5.3.2. Area Mapping 32.5.3.3. Packet Definition 32.5.3.3.1. Header Field 32.5.3.3.2. “Special” Packets 32.5.3.4. Init 32.5.3.5. Read Access 32.5.3.5.1. Transfer a Packet through the Host Key Bus 32.5.3.5.2. Hiding a Packet 32.5.3.6. Write (Program) Considerations 32.5.3.6.1. ‘1’ in the Header 32.5.3.6.2. ‘1’ in the Payload 32.5.3.7. Write (Program) Access 32.5.3.7.1. Writing a New Packet from the User Interface 32.5.3.7.2. Updating an Existing Packet from the User Interface 32.5.3.7.3. Writing a Packet from the Client Key Bus 32.5.3.7.4. Locking a Packet 32.5.3.7.5. Invalidating a Packet 32.5.3.8. Fixing Corruption 32.5.3.9. “Software” Protections 32.5.3.10. “Hardware” Protections 32.5.4. OTP Emulation Mode 32.5.5. Interrupts 32.5.6. Register Write Protection 32.6. Register Summary 32.6.1. OTPC Control Register 32.6.2. OTPC Mode Register 32.6.3. OTPC Address Register 32.6.4. OTPC Status Register 32.6.5. OTPC Interrupt Enable Register 32.6.6. OTPC Interrupt Disable Register 32.6.7. OTPC Interrupt Mask Register 32.6.8. OTPC Interrupt Status Register 32.6.9. OTPC Header Register 32.6.10. OTPC Data Register 32.6.11. OTPC Boot Addresses Register 32.6.12. OTPC Custom Address Register 32.6.13. OTPC Secure Custom Address Register 32.6.14. OTPC User Hardware Configuration 0 Register 32.6.15. OTPC User Hardware Configuration 1 Register 32.6.16. OTPC Product UID x Register 32.6.17. OTPC Write Protection Mode Register 32.6.18. OTPC Write Protection Status Register 33. Special Function Registers (SFR) 33.1. Description 33.2. Embedded Characteristics 33.3. Functional Description 33.3.1. Register Write Protection 33.4. Register Summary 33.4.1. OHCI Interrupt Configuration Register 33.4.2. OHCI Interrupt Status Register 33.4.3. SFR Write Protection Mode Register 33.4.4. SFR Write Protection Status Register 33.4.5. EHCIOHCI Register 33.4.6. SFR_HSS_AXIQOS 33.4.7. SFR_UDDRC 33.4.8. SFR CAN SRAM Selection Register 33.4.9. UTMI0 Configuration Register 34. Special Function Registers Backup (SFRBU) 34.1. Description 34.2. Embedded Characteristics 34.3. Register Summary 34.3.1. SFRBU Power Switch BU Control Register 34.3.2. SFRBU 2.5V LDO Control Register 34.3.3. SFRBU DDR Power Control Register 35. Slow Clock Controller (SCKC) 35.1. Description 35.2. Embedded Characteristics 35.3. Block Diagram 35.4. Functional Description 35.4.1. Switching from Embedded Always-on 64 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 35.4.2. Switching from 32.768 kHz Crystal Oscillator to Embedded Always-on 64 kHz RC Oscillator 35.5. Register Summary 35.5.1. Slow Clock Controller Configuration Register 36. Clock Generator 36.1. Description 36.2. Embedded Characteristics 36.3. Block Diagram 36.4. Slow Clock 36.4.1. Slow RC Oscillator (32 kHz typical) 36.4.2. 32.768 kHz Crystal Oscillator 36.5. Main Clock 36.5.1. Main RC Oscillator 36.5.2. Main Crystal Oscillator 36.5.3. Main Clock Source Selection 36.5.4. Bypassing the Main Crystal Oscillator 36.5.5. Main Frequency Counter 36.6. PLL Controls 36.6.1. Divider and Phase Lock Loop Programming 36.6.2. UTMI PLL 36.6.3. PLL Unlock 36.6.4. Spread Spectrum 37. Power Management Controller (PMC) 37.1. Description 37.2. Embedded Characteristics 37.3. Block Diagram 37.4. Processor Clock Controller 37.4.1. Processor Clock Ratio 37.5. Free-running Processor Clock 37.6. Main System Bus Clock Controller 37.7. Peripheral and Generic Clock Controller 37.8. Programmable Clock Output Controller 37.9. Ultra-Low Power Modes and Fast Start-Up 37.9.1. ULP1 and ULP2 Modes 37.9.2. Fast Start-Up 37.10. Asynchronous Partial Wake-Up 37.10.1. Description 37.10.2. Asynchronous Partial Wake-Up when System is in ULP1 Mode 37.10.2.1. Configuration Procedure 37.10.3. Asynchronous Partial Wake-Up of a Peripheral in Active Mode 37.10.3.1. Configuration Procedure 37.11. Main Crystal Oscillator Failure Detection 37.12. 32.768 kHz Crystal Oscillator Frequency Monitor 37.13. MCK0 Frequency Monitor 37.14. Recommended Programming Sequence 37.15. Clock Switching Details 37.15.1. CPU Clock Switching Timings 37.15.2. Main System Bus Clocks Switching Timings 37.16. Register Write Protection 37.17. Register Summary 37.17.1. PMC System Clock Enable Register 37.17.2. PMC System Clock Disable Register 37.17.3. PMC System Clock Status Register 37.17.4. PMC PLL Control Register 0 37.17.5. PMC PLL Control Register 1 37.17.6. PMC PLL Spread Spectrum Register 37.17.7. PMC PLL Analog Control Register 37.17.8. PMC PLL Update Register 37.17.9. PMC Clock Generator Main Oscillator Register 37.17.10. PMC Clock Generator Main Clock Frequency Register 37.17.11. PMC CPU Clock Register 37.17.12. PMC CPU Clock Ratio Register 37.17.13. PMC Main System Bus Clock Register 37.17.14. PMC_XTALF 37.17.15. PMC Programmable Clock Register 37.17.16. PMC Interrupt Enable Register 37.17.17. PMC Interrupt Disable Register 37.17.18. PMC Status Register 37.17.19. PMC Interrupt Mask Register 37.17.20. PMC Fast Start-Up Mode Register 37.17.21. PMC Wake-Up Control Register 37.17.22. PMC Fault Output Clear Register 37.17.23. PMC Write Protection Mode Register 37.17.24. PMC Write Protection Status Register 37.17.25. PMC Peripheral Control Register 37.17.26. PMC Asynchronous Partial Wake-Up Activity In Progress Register 37.17.27. PMC Asynchronous Partial Wake-Up Control Register 37.17.28. PMC MCK0 Monitor Limits Register 37.17.29. PMC Peripheral Clock Status Register 0 37.17.30. PMC Peripheral Clock Status Register 1 37.17.31. PMC Peripheral Clock Status Register 2 37.17.32. PMC Peripheral Clock Status Register 3 37.17.33. PMC Generic Clock Status Register 0 37.17.34. PMC Generic Clock Status Register 1 37.17.35. PMC Generic Clock Status Register 2 37.17.36. PMC PLL Interrupt Enable Register 37.17.37. PMC PLL Interrupt Disable Register 37.17.38. PMC PLL Interrupt Mask Register 37.17.39. PMC PLL Interrupt Status Register 0 37.17.40. PMC PLL Interrupt Status Register 1 38. Parallel Input/Output Controller (PIO) 38.1. Description 38.2. Embedded Characteristics 38.3. Block Diagram 38.4. Product Dependencies 38.4.1. Pin Multiplexing 38.4.2. External Interrupt Lines 38.4.3. Power Management 38.4.4. Interrupt Generation 38.5. Functional Description 38.5.1. I/O Line Configuration Method 38.5.1.1. Security Management 38.5.1.2. Programming I/O Line Configuration 38.5.1.3. Reading the I/O Line Configuration 38.5.2. Pull-Up and Pull-Down Resistor Control 38.5.3. General Purpose or Peripheral Function Selection 38.5.4. Output Control 38.5.5. Synchronous Data Output 38.5.6. Open-Drain Mode 38.5.7. Output Line Timings 38.5.8. Inputs 38.5.9. Input Glitch and Debouncing Filters 38.5.10. Input Edge/Level Interrupt 38.5.11. Interrupt Management 38.5.12. I/O Lines Lock 38.5.13. Programmable I/O Drive 38.5.14. Programmable Schmitt Trigger 38.5.15. Programmable Slew Rate 38.5.16. I/O Line Configuration Freeze 38.5.16.1. Introduction 38.5.16.2. Software Freeze 38.5.16.2.1. Physical Freeze 38.5.16.2.2. Interrupt Freeze 38.5.16.3. Tamper Freeze 38.5.17. Register Write Protection 38.6. I/O Lines Programming Example 38.7. Register Summary 38.7.1. PIO Mask Register 38.7.2. PIO Configuration Register 38.7.3. PIO Pin Data Status Register 38.7.4. PIO Lock Status Register 38.7.5. PIO Set Output Data Register 38.7.6. PIO Clear Output Data Register 38.7.7. PIO Output Data Status Register 38.7.8. PIO Interrupt Enable Register 38.7.9. PIO Interrupt Disable Register 38.7.10. PIO Interrupt Mask Register 38.7.11. PIO Interrupt Status Register 38.7.12. PIO I/O Freeze Configuration Register 38.7.13. PIO Tamper Freeze Register 38.7.14. PIO Write Protection Mode Register 38.7.15. PIO Write Protection Status Register 38.7.16. Secure PIO Mask Register 38.7.17. Secure PIO Configuration Register 38.7.18. Secure PIO Pin Data Status Register 38.7.19. Secure PIO Lock Status Register 38.7.20. Secure PIO Set Output Data Register 38.7.21. Secure PIO Clear Output Data Register 38.7.22. Secure PIO Output Data Status Register 38.7.23. Secure PIO Interrupt Enable Register 38.7.24. Secure PIO Interrupt Disable Register 38.7.25. Secure PIO Interrupt Mask Register 38.7.26. Secure PIO Interrupt Status Register 38.7.27. Secure PIO Set I/O Non-Secure Register 38.7.28. Secure PIO Set I/O Secure Register 38.7.29. Secure PIO I/O Security Status Register 38.7.30. Secure PIO I/O Freeze Configuration Register 38.7.31. Secure PIO Slow Clock Divider Debouncing Register 38.7.32. Secure PIO Tamper Freeze Register 38.7.33. Secure PIO Write Protection Mode Register 38.7.34. Secure PIO Write Protection Status Register 39. ANALOG SUBSYSTEM 39.1. Block Diagram 39.2. Components 39.3. Product Dependencies 39.3.1. Clocks 39.3.2. Interrupts 39.3.3. Reset 39.3.4. I/Os 39.4. Special Functions in SFR/SFRBU 40. Analog-to-Digital Converter (ADC) Controller 40.1. Description 40.2. Embedded Characteristics 40.3. Block Diagram 40.4. Product Dependencies 40.4.1. Power Management 40.4.2. Interrupt Sources 40.4.3. Battery Voltage 40.4.4. Temperature Sensor 40.4.5. I/O Lines 40.4.6. Hardware Triggers 40.4.7. Fault Output 40.5. Functional Description 40.5.1. Analog-to-Digital Conversion 40.5.2. ADC Clock 40.5.3. ADC Reference Voltage 40.5.4. Conversion Resolution 40.5.5. Conversion Results 40.5.6. Conversion Results Format 40.5.7. Conversion Triggers 40.5.8. Sleep Mode and Conversion Sequencer 40.5.9. Comparison Window 40.5.10. Differential and Single-ended Input Modes 40.5.10.1. Input-Output Transfer Functions 40.5.10.2. Alternate Multiplexer Selection (Safety) 40.5.11. ADC Timings 40.5.12. Temperature Sensor 40.5.13. Enhanced Resolution Mode and Digital Averaging Function 40.5.13.1. Enhanced Resolution Mode 40.5.13.2. Averaging Function Versus Trigger Events 40.5.14. Automatic Error Correction 40.5.14.1. Calibration Mode of Operation 40.5.14.1.1. First Conversion in ADCMODE=1 40.5.14.1.2. Second Conversion in ADCMODE=2 40.5.14.1.3. Third Conversion in ADCMODE=3 40.5.14.1.4. Final GAINCORR Computation 40.5.15. Buffer Structure without FIFO 40.5.15.1. Classic ADC Channels Only 40.5.16. Buffer Structure with FIFO 40.5.17. Fault Event 40.5.18. Register Write Protection 40.6. Register Summary 40.6.1. ADC Control Register 40.6.2. ADC Mode Register 40.6.3. ADC Channel Sequence Register 1 40.6.4. ADC Channel Sequence Register 2 40.6.5. ADC Channel Enable Register 40.6.6. ADC Channel Disable Register 40.6.7. ADC Channel Status Register 40.6.8. ADC Last Converted Data Register 40.6.9. ADC_LCDR (NO_OSR) 40.6.10. ADC Interrupt Enable Register 40.6.11. ADC Interrupt Disable Register 40.6.12. ADC Interrupt Mask Register 40.6.13. ADC Interrupt Status Register 40.6.14. ADC End Of Conversion Interrupt Enable Register 40.6.15. ADC End Of Conversion Interrupt Disable Register 40.6.16. ADC End Of Conversion Interrupt Mask Register 40.6.17. ADC End Of Conversion Interrupt Status Register 40.6.18. ADC Temperature Sensor Mode Register 40.6.19. ADC Temperature Compare Window Register 40.6.20. ADC Overrun Status Register 40.6.21. ADC Extended Mode Register 40.6.22. ADC Compare Window Register 40.6.23. ADC Channel Configuration Register 40.6.24. ADC Channel Data Register 40.6.25. ADC Analog Control Register 40.6.26. ADC FIFO Mode Register 40.6.27. ADC Trigger Register 40.6.28. ADC Correction Select Register 40.6.29. ADC Correction Values Register 40.6.30. ADC Channel Error Correction Register 40.6.31. ADC Write Protection Mode Register 40.6.32. ADC Write Protection Status Register 41. Analog Comparator Controller (ACC) 41.1. Description 41.2. Embedded Characteristics 41.3. Block Diagram 41.4. Signal Description 41.5. Product Dependencies 41.5.1. I/O Lines 41.5.2. Power Management 41.5.3. Interrupt Sources 41.5.4. Fault Output 41.6. Functional Description 41.6.1. Description 41.6.2. Fault Mode 41.6.3. Output Masking Period 41.6.4. Register Write Protection 41.7. Register Summary 41.7.1. ACC Control Register 41.7.2. ACC Mode Register 41.7.3. ACC Interrupt Enable Register 41.7.4. ACC Interrupt Disable Register 41.7.5. ACC Interrupt Mask Register 41.7.6. ACC Interrupt Status Register 41.7.7. ACC Analog Control Register 41.7.8. ACC Write Protection Mode Register 41.7.9. ACC Write Protection Status Register 42. IMAGE SUBSYSTEM 42.1. Block Diagram 42.2. Components 42.3. Product Dependencies 42.3.1. Clocks 42.3.2. Interrupts 42.3.3. Reset 42.3.4. I/Os 42.3.5. Power Saving 42.4. Special Functions in SFR/SFRBU 43. Camera Serial Interface (CSI) 43.1. Description 43.2. Embedded Characteristics 43.3. Signal Description 43.4. Block Diagram 43.5. Product Dependencies 43.5.1. Power Management 43.5.2. Interrupt Sources 43.6. Functional Description 43.6.1. D-PHY Operating Modes 43.6.1.1. Power-Up Mode 43.6.1.2. Shutdown Mode 43.6.1.3. Analog Initialization 43.6.1.4. Active Modes 43.6.1.4.1. Control Mode 43.6.1.4.2. High-Speed Data Reception Mode 43.6.1.4.3. Escape Mode 43.6.2. Supported Resolutions and Frame Rates 43.6.3. Descrambler 43.6.4. Interrupts 43.6.5. Error Detection 43.7. Register Summary 43.7.1. CSI Lane Configuration Register 43.7.2. CSI Reset Control Register 43.7.3. CSI Main Interrupt Status Register 43.7.4. CSI Data Identifier Register 1 43.7.5. CSI Data Identifier Register 2 43.7.6. CSI D-PHY Shutdown Register 43.7.7. CSI D-PHY Reset Register 43.7.8. CSI D-PHY Receive Status Register 43.7.9. CSI D-PHY Stop State Register 43.7.10. CSI D-PHY Analog Configuration Control Register 43.7.11. CSI D-PHY Analog Configuration Data Register 43.7.12. CSI D-PHY Calibration Status Register 43.7.13. CSI D-PHY Fatal Error Interrupt Status Register 43.7.14. CSI D-PHY Fatal Error Interrupt Mask Register 43.7.15. CSI Packet Fatal Error Interrupt Status Register 43.7.16. CSI Packet Fatal Error Interrupt Mask Register 43.7.17. CSI Frame Error Interrupt Status Register 43.7.18. CSI Frame Error Interrupt Mask Register 43.7.19. CSI D-PHY Interrupt Status Register 43.7.20. CSI D-PHY Interrupt Mask Register 43.7.21. CSI Virtual Channel Interrupt Status Register 43.7.22. CSI Virtual Channel Interrupt Mask Register 43.7.23. CSI Line Error Interrupt Status Register 43.7.24. CSI Line Interrupt Mask Register 43.7.25. CSI Descrambler Configuration Register 43.7.26. CSI Lane 0 Scrambling Seed Register 43.7.27. CSI Lane 1 Scrambling Seed Register 44. CSI-2 Demultiplexer Controller (CSI2DC) 44.1. Description 44.2. Embedded Characteristics 44.3. Block Diagram 44.4. I/O Lines Description 44.5. Functional Description 44.5.1. Image Data Snoop (IDS) Controller 44.5.2. Synchronization Short Packet Demux 44.5.3. Generic Short Packet Demux 44.5.4. Generic Long Packet Demux 44.5.5. YUV Packet Demux 44.5.5.1. YUV 420 8-bit Legacy Mode 44.5.5.2. YUV 420 8-bit Mode 44.5.5.3. YUV 420 10-bit Mode 44.5.5.4. YUV 422 8-bit Mode 44.5.5.5. YUV 422 10-bit Mode 44.5.6. RGB Packet Demux 44.5.6.1. RGB888 44.5.6.2. RGB666 44.5.6.3. RGB565 44.5.6.4. RGB555 44.5.6.5. RGB444 44.5.7. RAW Packet Demux 44.5.7.1. RAW6 44.5.7.2. RAW7 44.5.7.3. RAW8 44.5.7.4. RAW10 44.5.7.5. RAW12 44.5.7.6. RAW14 44.5.8. User-Defined 8-bit Data 44.5.9. CSI-2 Demux RAW Data Decompression Support 44.6. Register Summary 44.6.1. CSI2DC Global Configuration Register 44.6.2. CSI2DC Global Control Register 44.6.3. CSI2DC Global Status Register 44.6.4. CSI2DC Global Interrupt Enable Register 44.6.5. CSI2DC Global Interrupt Disable Register 44.6.6. CSI2DC Global Interrupt Mask Register 44.6.7. CSI2DC Global Interrupt Status Register 44.6.8. CSI2DC SSP Interrupt Enable Register 44.6.9. CSI2DC SSP Interrupt Disable Register 44.6.10. CSI2DC SSP Interrupt Mask Register 44.6.11. CSI2DC SSP Interrupt Status Register 44.6.12. CSI2DC Frame Number Virtual Channel 0 Register 44.6.13. CSI2DC Frame Number Virtual Channel 1 Register 44.6.14. CSI2DC Frame Number Virtual Channel 2 Register 44.6.15. CSI2DC Frame Number Virtual Channel 3 Register 44.6.16. CSI2DC Line Number Virtual Channel 0 Register 44.6.17. CSI2DC Line Number Virtual Channel 1 Register 44.6.18. CSI2DC Line Number Virtual Channel 2 Register 44.6.19. CSI2DC Line Number Virtual Channel 3 Register 44.6.20. CSI2DC GSP Interrupt Enable Register 44.6.21. CSI2DC GSP Interrupt Disable Register 44.6.22. CSI2DC GSP Interrupt Mask Register 44.6.23. CSI2DC GSP Interrupt Status Register 44.6.24. CSI2DC GSP Status 0 Register 44.6.25. CSI2DC GSP Status 1 Register 44.6.26. CSI2DC GSP Status 2 Register 44.6.27. CSI2DC GSP Status 3 Register 44.6.28. CSI2DC GLP Interrupt Enable Register 44.6.29. CSI2DC GLP Interrupt Disable Register 44.6.30. CSI2DC GLP Interrupt Mask Register 44.6.31. CSI2DC GLP Interrupt Status Register 44.6.32. CSI2DC IDS Control Register 44.6.33. CSI2DC IDS Interrupt Enable Register 44.6.34. CSI2DC IDS Interrupt Disable Register 44.6.35. CSI2DC IDS Interrupt Mask Register 44.6.36. CSI2DC IDS Interrupt Status Register 44.6.37. CSI2DC IDS Entry Word 0 Register 44.6.38. CSI2DC IDS Entry Word 1 Register 44.6.39. CSI2DC Pipe Update Register 44.6.40. CSI2DC Pipe Update Status Register 44.6.41. CSI2DC Data Pipe Interrupt Enable Register 44.6.42. CSI2DC Data Pipe Interrupt Disable Register 44.6.43. CSI2DC Data Pipe Interrupt Mask Register 44.6.44. CSI2DC Data Pipe Interrupt Status Register 44.6.45. CSI2DC Data Pipe Interrupt Clear Register 44.6.46. CSI2DC Data Pipe Enable Register 44.6.47. CSI2DC Data Pipe Configuration Register 44.6.48. CSI2DC Data Pipe DMA Configuration Register 44.6.49. CSI2DC Video Pipe Interrupt Enable Register 44.6.50. CSI2DC Video Pipe Interrupt Disable Register 44.6.51. CSI2DC Video Pipe Interrupt Mask Register 44.6.52. CSI2DC Video Pipe Interrupt Status Register 44.6.53. CSI2DC Video Pipe Enable Register 44.6.54. CSI2DC Video Pipe Configuration Register 44.6.55. CSI2DC Video Pipe Column Register 44.6.56. CSI2DC Video Pipe Row Register 44.6.57. CSI2DC Video Pipe Data Type Remap Register 45. Image Sensor Controller (ISC) 45.1. Description 45.2. Embedded Characteristics 45.3. Block Diagram and Use Cases 45.3.1. Functional Diagrams 45.4. I/O Lines Description 45.4.1. Clock Domain Diagram 45.4.2. Typical Use Cases 45.5. Product Dependencies 45.5.1. I/O Lines 45.5.2. Power Management 45.5.3. Interrupt Sources 45.6. Functional Description 45.6.1. ISC Clock Management 45.6.1.1. Software Requirement 45.6.2. Parallel Interface Timing Description 45.6.3. BT.601/656/1120 Embedded Timing Synchronization Operation 45.6.4. Parallel Interface External Sensor Connections 45.6.4.1. YCbCr, 10-bit CCIR656 with Embedded Synchronization 45.6.4.2. YCbCr, 8-bit CCIR656 with Embedded Synchronization 45.6.4.3. Raw Bayer Parallel Interface 45.6.4.4. Monochrome Parallel Interface 45.6.5. MIPI Interface Mapping 45.6.6. Parallel Front End (PFE) Module 45.6.6.1. Update the ISC Profile 45.6.6.2. Software Requirements 45.6.7. Defective Pixel Correction (DPC) 45.6.8. Green Disparity Correction (GDC) 45.6.9. Black Level Correction (BLC) 45.6.10. White Balance (WB) Module 45.6.11. Color Filter Array (CFA) Interpolation Module 45.6.11.1. Frame Size Requirement when Edge Interpolation is Off, ISC_CFA_CFG.EITPOL Cleared 45.6.11.2. Frame Size Requirement when Edge Interpolation is On, ISC_CFA_CFG.EITPOL Set 45.6.11.3. Bayer Mode and Edge Interpolation Description 45.6.12. Color Correction (CC) Module 45.6.13. Gamma Curve (GAM) Module 45.6.14. Color Space Conversion (CSC) Module 45.6.15. Contrast, Brightness, Hue and Saturation 45.6.16. 4:4:4 To 4:2:2 Chrominance Horizontal Subsampler (SUB422) Module 45.6.17. 4:2:2 To 4:2:0 Chrominance Vertical Subsampler (SUB420) Module 45.6.18. Rounding, Limiting and Packing (RLP) Module 45.6.19. DMA Interface 45.6.19.1. Descriptor Memory Address Mapping 45.6.19.2. Descriptor Memory Mapping 45.6.19.3. Example: Memory Mapping for 16-bit Packed, DMA Interface IMODE = 1 at ISC_DAD0.AD0 Location 45.6.19.4. Example: Memory Mapping for 12-bit YC420SP, DMA Interface IMODE = 5 45.6.19.5. Example: Memory Mapping for 12-bit YC420P, DMA Interface IMODE = 6 45.6.20. Histogram Module 45.7. Register Summary 45.7.1. ISC Control Enable Register 45.7.2. ISC Control Disable Register 45.7.3. ISC Control Status Register 45.7.4. ISC Parallel Front End Configuration 0 Register 45.7.5. ISC Parallel Front End Configuration 1 Register 45.7.6. ISC Parallel Front End Configuration 2 Register 45.7.7. ISC Clock Enable Register 45.7.8. ISC Clock Disable Register 45.7.9. ISC Clock Status Register 45.7.10. ISC Clock Configuration Register 45.7.11. ISC Interrupt Enable Register 45.7.12. ISC Interrupt Disable Register 45.7.13. ISC Interrupt Mask Register 45.7.14. ISC Interrupt Status Register 45.7.15. ISC Defective Pixel Control Register 45.7.16. ISC Defective Pixel Configuration Register 45.7.17. ISC Defective Pixel Correction Median Threshold Register 45.7.18. ISC Defective Pixel Correction Closest Threshold Register 45.7.19. ISC Defective Pixel Correction Average Threshold Register 45.7.20. ISC Defective Pixel Correction Status Register 45.7.21. ISC White Balance Control Register 45.7.22. ISC White Balance Configuration Register 45.7.23. ISC White Balance Offset for R, GR Register 45.7.24. ISC White Balance Offset for B and GB Register 45.7.25. ISC White Balance Gain for R, GR Register 45.7.26. ISC White Balance Gain for B, GB Register 45.7.27. ISC Color Filter Array Control Register 45.7.28. ISC Color Filter Array Configuration Register 45.7.29. ISC Color Correction Control Register 45.7.30. ISC Color Correction RR RG Register 45.7.31. ISC Color Correction RB OR Register 45.7.32. ISC Color Correction GR GG Register 45.7.33. ISC Color Correction GB OG Register 45.7.34. ISC Color Correction BR BG Register 45.7.35. ISC Color Correction BB OB Register 45.7.36. ISC Gamma Correction Control Register 45.7.37. ISC_GAM_BENTRYx 45.7.38. ISC Gamma Correction Green Entry Register x [x=0..63] 45.7.39. ISC Gamma Correction Red Entry Register x [x=0..63] 45.7.40. ISC_VHXS_CTRL 45.7.41. ISC_VHXS_SS 45.7.42. ISC_VHXS_DS 45.7.43. ISC_VXS_FACT 45.7.44. ISC_HXS_FACT 45.7.45. ISC_VXS_CFG 45.7.46. ISC_HXS_CFG 45.7.47. ISC_VXS_TAP10PHIx 45.7.48. ISC_VXS_TAP32PHIx 45.7.49. ISC_HXS_TAP10PHIx 45.7.50. ISC_HXS_TAP32PHIx 45.7.51. ISC Color Space Conversion Control Register 45.7.52. ISC Color Space Conversion YR YG Register 45.7.53. ISC Color Space Conversion YB OY Register 45.7.54. ISC Color Space Conversion CBR CBG Register 45.7.55. ISC Color Space Conversion CBB OCB Register 45.7.56. ISC Color Space Conversion CRR CRG Register 45.7.57. ISC Color Space Conversion CRB OCR Register 45.7.58. ISC_CBHS_CTRL 45.7.59. ISC_CBHS_CFG 45.7.60. ISC_CBHS_BRIGHT 45.7.61. ISC_CBHS_CONTRAST 45.7.62. ISC_CBHS_HUE 45.7.63. ISC_CBHS_SAT 45.7.64. ISC Subsampling 4:4:4 to 4:2:2 Control Register 45.7.65. ISC Subsampling 4:4:4 to 4:2:2 Configuration Register 45.7.66. ISC Subsampling 4:2:2 to 4:2:0 Control Register 45.7.67. ISC Rounding, Limiting and Packing Configuration Register 45.7.68. ISC Histogram Control Register 45.7.69. ISC Histogram Configuration Register 45.7.70. ISC DMA Configuration Register 45.7.71. ISC DMA Control Register 45.7.72. ISC DMA Descriptor Address Register 45.7.73. ISC DMA Address 0 Register 45.7.74. ISC DMA Stride 0 Register 45.7.75. ISC DMA Address 1 Register 45.7.76. ISC DMA Stride 1 Register 45.7.77. ISC DMA Address 2 Register 45.7.78. ISC DMA Stride 2 Register 45.7.79. ISC Histogram Entry x [x=0..511] 46. AUDIO SUBSYSTEM 46.1. Block Diagram 46.2. Components 46.3. Product Dependencies 46.3.1. Clocks 46.3.2. Interrupts 46.3.3. Reset 46.3.4. I/Os 46.4. Special Functions in SFR/SFRBU 47. Inter-IC Sound Multi-Channel Controller (I2SMCC) 47.1. Description 47.2. Embedded Characteristics 47.3. Block Diagram 47.4. I/O Lines Description 47.5. Product Dependencies 47.5.1. I/O Lines 47.5.2. Power Management 47.5.3. Clocks 47.5.4. DMA Controller 47.5.5. Interrupt Sources 47.6. Functional Description 47.6.1. Initialization 47.6.2. Basic Operation 47.6.3. Host, Controller and Client Modes 47.6.4. I2S Reception and Transmission Sequence 47.6.5. Left-Justified Reception and Transmission Sequence 47.6.6. TDM Reception and Transmission Sequence 47.6.7. Serial Clock and Word Select Generation 47.6.8. Mono 47.6.9. Wire Configurations 47.6.10. Holding Registers 47.6.10.1. Dedicated Registers 47.6.10.2. Common Registers 47.6.11. DMA Controller Operation 47.6.12. Loop-back Mode 47.6.13. Interrupts 47.6.14. Register Write Protection 47.6.15. Functional Safety (Protection, Monitors and Reports) 47.6.15.1. Protections 47.6.15.2. Monitors and Reports 47.7. Register Summary 47.7.1. I2SMCC Control Register 47.7.2. I2SMCC Mode Register A 47.7.3. I2SMCC Mode Register B 47.7.4. I2SMCC Status Register 47.7.5. I2SMCC Interrupt Enable Register A 47.7.6. I2SMCC Interrupt Disable Register A 47.7.7. I2SMCC Interrupt Mask Register A 47.7.8. I2SMCC Interrupt Status Register A 47.7.9. I2SMCC Interrupt Enable Register B 47.7.10. I2SMCC Interrupt Disable Register B 47.7.11. I2SMCC Interrupt Mask Register B 47.7.12. I2SMCC Interrupt Status Register B 47.7.13. I2SMCC Receiver Holding Register 47.7.14. I2SMCC Transmitter Holding Register 47.7.15. I2SMCC Receiver Holding Left x Register 47.7.16. I2SMCC Receiver Holding Right x Register 47.7.17. I2SMCC Transmitter Holding Left x Register 47.7.18. I2SMCC Transmitter Holding Right x Register 47.7.19. I2SMCC Write Protection Mode Register 47.7.20. I2SMCC Write Protection Status Register 48. Synchronous Serial Controller (SSC) 48.1. Description 48.2. Embedded Characteristics 48.3. Block Diagram 48.4. Application Block Diagram 48.5. SSC Application Examples 48.6. Pin Name List 48.7. Product Dependencies 48.7.1. I/O Lines 48.7.2. Power Management 48.7.3. Interrupt 48.8. Functional Description 48.8.1. Clock Management 48.8.1.1. Clock Divider 48.8.1.2. Transmit Clock Management 48.8.1.3. Receive Clock Management 48.8.1.4. Serial Clock Ratio Considerations 48.8.2. Transmit Operations 48.8.3. Receive Operations 48.8.4. Start 48.8.5. Frame Synchronization 48.8.5.1. Frame Sync Data 48.8.5.2. Frame Sync Edge Detection 48.8.6. Receive Compare Modes 48.8.6.1. Compare Functions 48.8.7. Data Format 48.8.8. Loop Mode 48.8.9. Interrupt 48.8.10. Register Write Protection 48.9. Register Summary 48.9.1. SSC Control Register 48.9.2. SSC Clock Mode Register 48.9.3. SSC Receive Clock Mode Register 48.9.4. SSC Receive Frame Mode Register 48.9.5. SSC Transmit Clock Mode Register 48.9.6. SSC Transmit Frame Mode Register 48.9.7. SSC Receive Holding FIFO Register 48.9.8. SSC Transmit Holding FIFO Register 48.9.9. SSC_FFMR 48.9.10. SSC Receive Synchronization Holding Register 48.9.11. SSC Transmit Synchronization Holding Register 48.9.12. SSC Receive Compare 0 Register 48.9.13. SSC Receive Compare 1 Register 48.9.14. SSC Status Register 48.9.15. SSC Interrupt Enable Register 48.9.16. SSC Interrupt Disable Register 48.9.17. SSC Interrupt Mask Register 48.9.18. SSC Write Protection Mode Register 48.9.19. SSC Write Protection Status Register 49. Sony/Philips Digital Interface Receiver (SPDIFRX) 49.1. Description 49.2. Embedded Characteristics 49.3. Block Diagram 49.4. Signal Description 49.5. Product Dependencies 49.5.1. I/O Lines 49.5.2. Power Management 49.5.3. Interrupt Sources 49.6. Functional Description 49.6.1. Protocol 49.6.2. Data Rate 49.6.3. Clock and Data Recovery 49.6.4. Sample Frequency Measurement 49.6.5. Data Management 49.6.6. FIFO Organization 49.6.7. Channel Status Bit 49.6.8. User Data Bit 49.6.9. Write Protection Registers 49.7. Register Summary 49.7.1. SPDIF Receiver Control Register 49.7.2. SPDIF Receiver Mode Register 49.7.3. SPDIF Receiver Interrupt Enable Register 49.7.4. SPDIF Receiver Interrupt Disable Register 49.7.5. SPDIF Receiver Interrupt Mask Register 49.7.6. SPDIF Receiver Interrupt Status Register 49.7.7. SPDIF Receiver Status Register 49.7.8. SPDIF Receiver Holding Register 49.7.9. SPDIF Receiver Channel 1 Channel Status Register 49.7.10. SPDIF Receiver Channel 1 User Data Register 49.7.11. SPDIF Receiver Channel 2 Channel Status Register 49.7.12. SPDIF Receiver Channel 2 User Data Register 49.7.13. SPDIF Receiver Write Protection Mode Register 49.7.14. SPDIF Receiver Write Protection Status Register 50. Sony/Philips Digital Interface Transmitter (SPDIFTX) 50.1. Description 50.2. Embedded Characteristics 50.3. Block Diagram 50.4. Signal Description 50.5. Product Dependencies 50.5.1. I/O Lines 50.5.2. Power Management 50.5.3. Interrupt Sources 50.6. Functional Description 50.6.1. SPDIF Transmitter Transmission 50.6.1.1. SPDIF Protocol 50.6.1.2. SPDIF Transmitter Data Rate 50.6.2. SPDIF Transmitter FIFO 50.6.3. Data Organization 50.6.3.1. Automatic Data Alignment 50.6.3.2. Up to 8-bit Data 50.6.3.3. 9-bit to 16-bit Data 50.6.3.4. 17-bit to 24-bit Data 50.6.3.5. 25-bit to 32-bit Data 50.6.4. Channel Status and User Data Bits in SPDIF Frame 50.6.4.1. Direct Mapping Registers 50.6.4.2. Frame-Oriented Configuration 50.6.5. Transmit FIFO 50.6.6. Write Protection Registers 50.7. Register Summary 50.7.1. SPDIF Transmitter Control Register 50.7.2. SPDIF Transmitter Mode Register 50.7.3. SPDIFTX_EMR 50.7.4. SPDIF Transmitter Common Data Register 50.7.5. SPDIFTX_CDR (CONTROL_BITS) 50.7.6. SPDIFTX_SR 50.7.7. SPDIF Transmitter Interrupt Enable Register 50.7.8. SPDIF Transmitter Interrupt Disable Register 50.7.9. SPDIF Transmitter Interrupt Mask Register 50.7.10. SPDIF Transmitter Interrupt Status Register 50.7.11. SPDIFTX_SFI 50.7.12. SPDIFTX_AW1 50.7.13. SPDIFTX_AW2 50.7.14. SPDIFTX_CH1UDx 50.7.15. SPDIFTX_CH2UDx 50.7.16. SPDIFTX_CH1Sx 50.7.17. SPDIFTX_CH2Sx 50.7.18. SPDIFTX_WPMR 50.7.19. SPDIFTX_WPSR 51. Pulse Density Microphone Controller (PDMC) 51.1. Description 51.2. Embedded Characteristics 51.3. PDMC Block Diagram 51.4. Signal Description 51.5. Product Dependencies 51.5.1. Power Management 51.5.2. Interrupt Sources 51.6. Functional Description 51.6.1. Clocks and Output Sampling Rate 51.6.2. SINC Filter 51.6.3. Audio Filter 51.6.4. Input Muxing 51.6.5. Receive Channel 51.6.6. Register Write Protection 51.7. Register Summary 51.7.1. PDMC Control Register 51.7.2. PDMC Mode Register 51.7.3. PDMC Configuration Register 51.7.4. PDMC Receive Holding Register 51.7.5. PDMC Interrupt Enable Register 51.7.6. PDMC Interrupt Disable Register 51.7.7. PDMC Interrupt Mask Register 51.7.8. PDMC Interrupt Status Register 51.7.9. PDMC Write Protection Mode Register 51.7.10. PDMC Write Protection Status Register 52. Asynchronous Sample Rate Converter (ASRC) 52.1. Embedded Characteristics 52.2. Description 52.3. Block Diagram 52.4. Product Dependencies 52.4.1. Power Management 52.4.2. Interrupt Sources 52.5. Functional Description 52.5.1. Preamble 52.5.2. Limitations 52.5.3. Sampling Frequencies and Oversampling 52.5.4. Embedded Digital PLL 52.5.5. DSP and Channel Configuration 52.5.5.1. Transmit Channel 52.5.5.2. Receive Channel 52.5.5.3. Data Format 52.5.6. TDM Audio Stream Management 52.5.7. Configuration Limitations 52.5.8. Initialization Sequence 52.5.9. Application Example 52.5.10. Channels Split/Merge Capability 52.5.11. Register Write Protection 52.6. Register Summary 52.6.1. ASRC Control Register 52.6.2. ASRC Mode Register 52.6.3. ASRC Ratio Register of Stereo Channel x 52.6.4. ASRC Valid bit Per Sample In Register 52.6.5. ASRC Valid bit Per Sample Out Register 52.6.6. ASRC Channel Configuration Register 52.6.7. ASRC Trigger Selection Register 52.6.8. ASRC Receive Holding Register of Stereo Channel x 52.6.9. ASRC Transmit Holding Register of Channel x 52.6.10. ASRC Interrupt Enable Register of Stereo Channel x 52.6.11. ASRC Interrupt Disable Register of Stereo Channel x 52.6.12. ASRC Interrupt Mask Register of Stereo Channel x 52.6.13. ASRC Interrupt Status Register of Stereo Channel x 52.6.14. ASRC Error Status Register 52.6.15. ASRC Write Protection Mode Register 52.6.16. ASRC Write Protection Status Register 53. CRYPTOGRAPHY SUBSYSTEM 53.1. Block Diagram 53.2. Components 53.2.1. Cryptography Subsystem Keybus 53.3. Product Dependencies 53.3.1. Clocks 53.3.2. Interrupts 53.3.3. Reset 53.3.4. I/Os 53.4. Special Functions in SFR/SFRBU 54. TrustZone Advanced Encryption Standard Bridge (TZAESB) 54.1. Description 54.2. Embedded Characteristics 54.3. Block Diagram 54.4. Product Dependencies 54.4.1. Power Management 54.4.2. Interrupt 54.5. Functional Description 54.5.1. TrustZone Security Attributes 54.5.2. Automatic Bridge Mode 54.5.2.1. Description 54.5.2.2. Configuration 54.5.3. Security Features 54.5.3.1. Private Key Bus 54.5.3.2. Unspecified Register Access Detection 54.5.3.3. Clearing Key on Tamper Event 54.5.3.4. Register Write Protection 54.5.3.5. Security and Safety Analysis and Reports 54.6. Register Summary 54.6.1. TZAESB Control Register 54.6.2. TZAESB_MR 54.6.3. TZAESB Interrupt Enable Register 54.6.4. TZAESB Interrupt Disable Register 54.6.5. TZAESB Interrupt Mask Register 54.6.6. TZAESB Interrupt Status Register 54.6.7. TZAESB Key Word Register x 54.6.8. TZAESB Initialization Vector Register x 54.6.9. TZAESB Extended Mode Register 54.6.10. TZAESB Write Protection Mode Register 54.6.11. TZAESB Write Protection Status Register 55. TrustZone AES Bridge Address Space Controller (TZAESBASC) 55.1. Description 55.2. Embedded Characteristics 55.3. Block Diagram 55.4. Functional Description 55.4.1. Operating Modes 55.4.2. Write Protection Registers 55.5. Register Summary 55.5.1. TZAESBASC Region x Base Address Register 55.5.2. TZAESBASC Region x Top Address Register 55.5.3. TZAESBASC Region Security Register 55.5.4. TZAESBASC Region Enable Register 55.5.5. TZAESBASC Region Disable Register 55.5.6. TZAESBASC Region Status Register 55.5.7. TZAESBASC Region Error Status Register 55.5.8. TZAESBASC Region Synchronization Status Register 55.5.9. TZAESBASC_WPMR 55.5.10. TZAESBASC_WPSR 56. Advanced Encryption Standard (AES) 56.1. Description 56.2. Embedded Characteristics 56.3. Product Dependencies 56.3.1. Power Management 56.3.2. Interrupt Sources 56.4. Functional Description 56.4.1. AES Register Endianness 56.4.2. Operating Modes 56.4.3. Last Output Data Mode (CBC-MAC) 56.4.3.1. Manual and Auto Modes 56.4.3.1.1. If AES_MR.LOD = 0 56.4.3.1.2. If AES_MR.LOD = 1 56.4.3.2. DMA Mode 56.4.3.2.1. If AES_MR.LOD = 0 56.4.3.2.2. If AES_MR.LOD = 1 56.4.4. Galois/Counter Mode (GCM) 56.4.4.1. Description 56.4.4.2. Key Writing and Automatic Hash Subkey Calculation 56.4.4.3. GCM Processing 56.4.4.3.1. Processing a Complete Message with Tag Generation 56.4.4.3.2. Processing a Complete Message without Tag Generation 56.4.4.3.3. Processing a Fragmented Message without Tag Generation 56.4.4.3.4. Manual GCM Tag Generation 56.4.4.3.5. Processing a Message with only AAD (GHASHH) 56.4.4.3.6. Processing a Single GF128 Multiplication 56.4.5. XEX-based Tweaked-codebook Mode (XTS) 56.4.5.1. XTS Processing Procedure 56.4.5.1.1. Encrypted Tweak Generation 56.4.5.1.2. Data Processing 56.4.6. Double Input Buffer 56.4.7. Temporary Secured Storage for Keys 56.4.8. Start Modes 56.4.8.1. Manual Mode 56.4.8.2. Auto Mode 56.4.8.3. DMA Mode 56.4.9. Automatic Padding Mode 56.4.9.1. IPSec Padding 56.4.9.2. SSL Padding 56.4.9.3. Flags 56.4.10. Secure Protocol Layers Improved Performances 56.4.10.1. Cipher Mode 56.4.10.2. Decipher Mode 56.4.10.3. Encapsulating Security Payload (ESP) IPSec Examples 56.4.11. Security Features 56.4.11.1. Private Key Bus 56.4.11.2. Unspecified Register Access Detection 56.4.11.3. Clearing Key on Tamper Event 56.4.11.4. Register Write Protection 56.4.11.5. Security and Safety Analysis and Reports 56.5. Register Summary 56.5.1. AES Control Register 56.5.2. AES Mode Register 56.5.3. AES Interrupt Enable Register 56.5.4. AES Interrupt Disable Register 56.5.5. AES Interrupt Mask Register 56.5.6. AES Interrupt Status Register 56.5.7. AES Key Word Register x 56.5.8. AES Input Data Register x 56.5.9. AES Output Data Register x 56.5.10. AES Initialization Vector Register x 56.5.11. AES Additional Authenticated Data Length Register 56.5.12. AES Plaintext/Ciphertext Length Register 56.5.13. AES GCM Intermediate Hash Word Register x 56.5.14. AES GCM Authentication Tag Word Register x 56.5.15. AES GCM Encryption Counter Value Register 56.5.16. AES GCM H Word Register x 56.5.17. AES Extended Mode Register 56.5.18. AES Byte Counter Register 56.5.19. AES Tweak Word Register x 56.5.20. AES Alpha Word Register x 56.5.21. AES Write Protection Mode Register 56.5.22. AES Write Protection Status Register 57. Secure Hash Algorithm (SHA) 57.1. Description 57.2. Embedded Characteristics 57.3. Product Dependencies 57.3.1. Power Management 57.3.2. Interrupt Sources 57.4. Functional Description 57.4.1. SHA Algorithm 57.4.2. HMAC Algorithm 57.4.3. Processing Period 57.4.4. Double Input Buffer 57.4.5. Internal Registers for Initial Hash Value or Expected Hash Result 57.4.6. Automatic Padding 57.4.7. Automatic Check 57.4.8. Protocol Layers Improved Performances 57.4.9. Start Modes 57.4.9.1. Manual Mode 57.4.9.2. Auto Mode 57.4.9.3. DMA Mode 57.4.9.4. SHA Register Endianness 57.4.10. Security Features 57.4.10.1. Unspecified Register Access Detection 57.4.10.2. Register Write Protection 57.4.10.3. Security and Safety Analysis and Reports 57.5. Register Summary 57.5.1. SHA Control Register 57.5.2. SHA Mode Register 57.5.3. SHA Interrupt Enable Register 57.5.4. SHA Interrupt Disable Register 57.5.5. SHA Interrupt Mask Register 57.5.6. SHA Interrupt Status Register 57.5.7. SHA Message Size Register 57.5.8. SHA Bytes Count Register 57.5.9. SHA Input Data Register x 57.5.10. SHA Input/Output Data Register x 57.5.11. SHA Write Protection Mode Register 57.5.12. SHA Write Protection Status Register 58. Triple Data Encryption Standard (TDES) 58.1. Description 58.2. Embedded Characteristics 58.3. Product Dependencies 58.3.1. Power Management 58.3.2. Interrupt Sources 58.4. Functional Description 58.4.1. Operating Modes 58.4.2. Temporary Secured Storage for Keys 58.4.3. Start Modes 58.4.3.1. Manual Mode 58.4.3.2. Auto Mode 58.4.3.3. DMA Mode 58.4.4. Last Output Data Mode (CBC-MAC) 58.4.4.1. Manual and Auto Modes 58.4.4.1.1. TDES_MR.LOD = 0 58.4.4.1.2. TDES_MR.LOD = 1 58.4.4.2. DMA Mode 58.4.4.2.1. TDES_MR.LOD = 0 58.4.4.2.2. TDES_MR.LOD = 1 58.4.5. Security Features 58.4.5.1. Private Key Bus 58.4.5.2. Unspecified Register Access Detection 58.4.5.3. Clearing Key on Tamper Event 58.4.5.4. Register Write Protection 58.4.5.5. Security and Safety Analysis and Reports 58.5. Register Summary 58.5.1. TDES Control Register 58.5.2. TDES Mode Register 58.5.3. TDES Interrupt Enable Register 58.5.4. TDES Interrupt Disable Register 58.5.5. TDES Interrupt Mask Register 58.5.6. TDES Interrupt Status Register 58.5.7. TDES Key 1 Word Register y 58.5.8. TDES Key 2 Word Register y 58.5.9. TDES Key 3 Word Register y 58.5.10. TDES Input Data Register x 58.5.11. TDES Output Data Register x 58.5.12. TDES Initialization Vector Register x 58.5.13. TDES XTEA Rounds Register 58.5.14. TDES Write Protection Mode Register 58.5.15. TDES Write Protection Status Register 59. True Random Number Generator (TRNG) 59.1. Description 59.2. Embedded Characteristics 59.3. Block Diagram 59.4. Product Dependencies 59.4.1. Power Management 59.4.2. Interrupt Sources 59.5. Functional Description 59.5.1. First Value Read after Power-up 59.5.2. Entropy 59.5.3. Register Write Protection 59.5.4. Security and Functional Analysis and Reports 59.6. Register Summary 59.6.1. TRNG Control Register 59.6.2. TRNG Mode Register 59.6.3. TRNG Private Key Bus Control Register 59.6.4. TRNG Interrupt Enable Register 59.6.5. TRNG Interrupt Disable Register 59.6.6. TRNG Interrupt Mask Register 59.6.7. TRNG Interrupt Status Register 59.6.8. TRNG Output Data Register 59.6.9. TRNG Write Protection Mode Register 59.6.10. TRNG Write Protection Status Register 60. Integrity Check Monitor (ICM) 60.1. Description 60.2. Embedded Characteristics 60.3. Block Diagram 60.4. Product Dependencies 60.4.1. Power Management 60.4.2. Interrupt Sources 60.5. Functional Description 60.5.1. Overview 60.5.2. ICM Region Descriptor Structure 60.5.2.1. ICM_RADDR 60.5.2.2. ICM_RCFG 60.5.2.3. ICM_RCTRL 60.5.2.4. ICM_RNEXT 60.5.3. ICM Hash Area 60.5.3.1. Message Digest Example 60.5.4. Using ICM as SHA Engine 60.5.4.1. Settings for Simple SHA Calculation 60.5.4.2. Processing Period 60.5.5. ICM Automatic Monitoring Mode 60.5.6. Programming the ICM 60.5.7. Security Features 60.5.8. ICM Register Write Protection 60.6. Register Summary 60.6.1. ICM Configuration Register 60.6.2. ICM Control Register 60.6.3. ICM Status Register 60.6.4. ICM Interrupt Enable Register 60.6.5. ICM Interrupt Disable Register 60.6.6. ICM Interrupt Mask Register 60.6.7. ICM Interrupt Status Register 60.6.8. ICM Undefined Access Status Register 60.6.9. ICM Descriptor Area Start Address Register 60.6.10. ICM Hash Area Start Address Register 60.6.11. ICM User Initial Hash Value Register 60.6.12. ICM Write Protection Mode Register 60.6.13. ICM Write Protection Status Register 61. Classical Public Key Cryptography Controller (CPKCC) 61.1. Description 61.2. Product Dependencies 61.2.1. Power Management 61.2.2. Interrupt Sources 61.3. Functional Description 62. Security Module (SECUMOD) 62.1. Description 62.2. Embedded Characteristics 62.3. Block Diagram 62.4. I/O Lines Description 62.5. Product Dependencies 62.5.1. Interrupt Sources 62.6. Functional Description 62.6.1. Memory Mapping 62.6.2. Scrambling Keys 62.6.3. Protection Mechanisms 62.6.3.1. Protection Manager 62.6.3.2. Test and JTAG Pin Monitor 62.6.3.3. PIO Backup Controller 62.6.3.3.1. Output Mode 62.6.3.3.2. Input Mode 62.6.3.3.3. Static Intrusion Detectors and Programmable Internal Pull-up/Pull-down 62.6.3.3.4. Static Intrusion Detection 62.6.3.3.5. Internal Pull-Up/Pull-Down 62.6.3.3.6. Scheduled Pull-Up/Pull-Down 62.6.3.3.7. Debouncing Time 62.6.3.3.8. PIOBUx Alarm Filtering in Static Mode 62.6.3.3.9. Dynamic Intrusions 62.6.3.3.9.1. Principle 62.6.3.3.9.2. Enabling Dynamic Detection 62.6.3.3.9.3. Tuning Dynamic Detection 62.6.3.3.9.4. External Filtering in Dynamic Mode 62.6.3.4. JTAG Prevention 62.6.3.4.1. Debug Interface Access Prevention 62.6.3.4.2. Physical Prevention for JTAG Debug 62.6.3.4.3. Physical Restrictions for JTAG Debug Mode 62.6.3.4.4. Software Prevention for JTAG Debug 62.6.3.4.5. Software Restrictions for JTAG Debug Mode 62.6.3.5. Voltage Monitors 62.6.3.5.1. VDDCORE Voltage Monitor Characteristics 62.6.3.5.2. VDDCORE Alarm Filtering 62.6.3.5.3. VDDCPU Voltage Monitor Characteristics 62.6.3.5.4. VDDCPU Alarm Filtering 62.6.3.5.5. VBAT and VDDBU Alarm Filtering 62.6.3.5.6. VDDANA Alarm 62.6.3.6. Temperature Monitor 62.6.3.7. Double Frequency Monitor 62.6.4. Non-Imprinting 62.6.4.1. Principle 62.6.4.2. Conditions Enabling or Disabling the Non-Imprinting Process 62.6.4.3. Granting System Access After Going Out of Imprinting Conditions 62.6.5. Erasing Secure Memories 62.6.5.1. BUSRAM4KB Erase Sequence 62.6.5.2. BUREG256b Erase Sequence 62.6.5.3. During and After BUSRAM4KB and BUREG256b Erase Sequence 62.6.5.4. Scrambling Key Protections 62.6.6. Operating Modes 62.6.6.1. Normal Mode 62.6.6.2. Backup Mode 62.6.6.2.1. Backup Mode Configuration 62.6.6.3. Automatic Backup Mode 62.6.7. Activation or Deactivation of Protections 62.6.8. Power-up Reset 62.7. Register Summary 62.7.1. SECUMOD Control Register 62.7.2. SECUMOD System Status Register 62.7.3. SECUMOD Status Register 62.7.4. SECUMOD Auxiliary Status Register 62.7.5. SECUMOD Status Clear Register 62.7.6. SECUMOD RAM Access Ready Register 62.7.7. SECUMOD PIO Backup Register x 62.7.8. SECUMOD_VBUFR 62.7.9. SECUMOD_VCOREFR 62.7.10. SECUMOD_VCPUFR 62.7.11. SECUMOD JTAG Protection Control Register 62.7.12. SECUMOD Dynamic Signatures Tuning Register 62.7.13. SECUMOD Scrambling Key Register 62.7.14. SECUMOD RAM Access Rights Register 62.7.15. SECUMOD RAM Access Rights Status Register 62.7.16. SECUMOD Backup Mode Protection Register 62.7.17. SECUMOD Normal Mode Protection Register 62.7.18. SECUMOD Normal Interrupt Enable Protection Register 62.7.19. SECUMOD Normal Interrupt Disable Protection Register 62.7.20. SECUMOD Normal Interrupt Mask Protection Register 62.7.21. SECUMOD Wake-up Register 62.7.22. SECUMOD General Purpose Security Bits Register 63. CONNECTIVITY SUBSYSTEM 63.1. Block Diagram 63.2. Components 63.3. FLEXCOM Features 63.4. Product Dependencies 63.4.1. Clocks 63.4.1.1. QSPI Features 63.4.1.2. GMAC Features 63.4.2. Interrupts 63.4.3. Reset 63.4.4. I/Os 63.4.4.1. GMAC I/Os 63.4.4.2. QSPI I/Os 63.5. Special Functions in SFR/SFRBU 64. Gigabit Ethernet MAC (GMAC) 64.1. Description 64.2. Embedded Characteristics 64.3. Block Diagram 64.4. Signal Interfaces 64.5. Product Dependencies 64.5.1. I/O Lines 64.5.2. Power Management 64.5.3. Interrupt Sources 64.6. Functional Description 64.6.1. Media Access Controller 64.6.2. 1588 Timestamp Unit 64.6.3. Direct Memory Access Interface 64.6.3.1. Packet Buffer DMA 64.6.3.2. Partial Store and Forward Using Packet Buffer DMA 64.6.3.3. Receive Buffers 64.6.3.4. Transmit Buffers 64.6.3.5. DMA Bursting on the System Bus 64.6.3.6. DMA Packet Buffer 64.6.3.7. Transmit Packet Buffer 64.6.3.8. Receive Packet Buffer 64.6.3.9. Priority Queueing in the DMA 64.6.4. MAC Transmit Block 64.6.5. Transmit Scheduling Algorithm 64.6.5.1. Introduction 64.6.5.2. 802.1Qav Support - Credit-based Shaping 64.6.5.3. Fixed Priority 64.6.5.4. Deficit Weighted Round Robin (DWRR) 64.6.5.5. Enhanced Transmission Selection (ETS) 64.6.6. MAC Receive Block 64.6.7. Checksum Offload for IP, TCP and UDP 64.6.7.1. Receiver Checksum Offload 64.6.7.2. Transmitter Checksum Offload 64.6.8. MAC Filtering Block 64.6.9. Broadcast Address 64.6.10. Hash Addressing 64.6.11. Copy all Frames (Promiscuous Mode) 64.6.12. Disable Copy of Pause Frames 64.6.13. VLAN Support 64.6.14. Wake on LAN Support 64.6.15. IEEE 1588 Support 64.6.16. MAC 802.3 Pause Frame Support 64.6.16.1. 802.3 Pause Frame Reception 64.6.16.2. 802.3 Pause Frame Transmission 64.6.17. MAC PFC Priority-based Pause Frame Support 64.6.17.1. PFC Pause Frame Reception 64.6.17.2. PFC Pause Frame Transmission 64.6.18. Energy-efficient Ethernet Support 64.6.19. LPI Operation in the GMAC 64.6.20. PHY Interface 64.6.21. 10/100/1000 Operation 64.6.22. Jumbo Frames 64.7. Programming Interface 64.7.1. Initialization 64.7.1.1. Configuration 64.7.1.2. Receive Buffer List 64.7.1.3. Transmit Buffer List 64.7.1.4. Address Matching 64.7.1.5. PHY Maintenance 64.7.1.6. Interrupts 64.7.1.7. Transmitting Frames 64.7.1.8. Receiving Frames 64.7.2. Statistics Registers 64.8. Register Summary 64.8.1. GMAC Network Control Register 64.8.2. GMAC Network Configuration Register 64.8.3. GMAC Network Status Register 64.8.4. GMAC User Register 64.8.5. GMAC DMA Configuration Register 64.8.6. GMAC Transmit Status Register 64.8.7. GMAC Receive Buffer Queue Base Address Register 64.8.8. GMAC Transmit Buffer Queue Base Address Register 64.8.9. GMAC Receive Status Register 64.8.10. GMAC Interrupt Status Register 64.8.11. GMAC Interrupt Enable Register 64.8.12. GMAC Interrupt Disable Register 64.8.13. GMAC Interrupt Mask Register 64.8.14. GMAC PHY Maintenance Register 64.8.15. GMAC Receive Pause Quantum Register 64.8.16. GMAC Transmit Pause Quantum Register 64.8.17. GMAC TX Partial Store and Forward Register 64.8.18. GMAC RX Partial Store and Forward Register 64.8.19. GMAC RX Jumbo Frame Max Length Register 64.8.20. GMAC_AMP 64.8.21. GMAC_INTM 64.8.22. GMAC_SYSWT 64.8.23. GMAC Hash Register Bottom 64.8.24. GMAC Hash Register Top 64.8.25. GMAC Specific Address 1 Bottom Register 64.8.26. GMAC Specific Address 1 Top Register 64.8.27. GMAC Specific Address 2 Bottom Register 64.8.28. GMAC Specific Address 2 Top Register 64.8.29. GMAC Specific Address 3 Bottom Register 64.8.30. GMAC Specific Address 3 Top Register 64.8.31. GMAC Specific Address 4 Bottom Register 64.8.32. GMAC Specific Address 4 Top Register 64.8.33. GMAC Type ID Match 1 Register 64.8.34. GMAC Type ID Match 2 Register 64.8.35. GMAC Type ID Match 3 Register 64.8.36. GMAC Type ID Match 4 Register 64.8.37. GMAC Wake on LAN Register 64.8.38. GMAC IPG Stretch Register 64.8.39. GMAC Stacked VLAN Register 64.8.40. GMAC Transmit PFC Pause Register 64.8.41. GMAC Specific Address 1 Mask Bottom Register 64.8.42. GMAC Specific Address Mask 1 Top Register 64.8.43. Address Mask for RX Data Buffer Accesses Register 64.8.44. PTP RX Unicast IP Destination Address Register 64.8.45. PTP TX Unicast IP Destination Address Register 64.8.46. GMAC 1588 Timer Nanosecond Comparison Register 64.8.47. GMAC 1588 Timer Second Comparison Low Register 64.8.48. GMAC 1588 Timer Second Comparison High Register 64.8.49. GMAC PTP Event Frame Transmitted Seconds High Register 64.8.50. GMAC PTP Event Frame Received Seconds High Register 64.8.51. GMAC PTP Peer Event Frame Transmitted Seconds High Register 64.8.52. GMAC PTP Peer Event Frame Received Seconds High Register 64.8.53. GMAC Octets Transmitted Low Register 64.8.54. GMAC Octets Transmitted High Register 64.8.55. GMAC Frames Transmitted Register 64.8.56. GMAC Broadcast Frames Transmitted Register 64.8.57. GMAC Multicast Frames Transmitted Register 64.8.58. GMAC Pause Frames Transmitted Register 64.8.59. GMAC 64 Byte Frames Transmitted Register 64.8.60. GMAC 65 to 127 Byte Frames Transmitted Register 64.8.61. GMAC 128 to 255 Byte Frames Transmitted Register 64.8.62. GMAC 256 to 511 Byte Frames Transmitted Register 64.8.63. GMAC 512 to 1023 Byte Frames Transmitted Register 64.8.64. GMAC 1024 to 1518 Byte Frames Transmitted Register 64.8.65. GMAC Greater Than 1518 Byte Frames Transmitted Register 64.8.66. GMAC Transmit Underruns Register 64.8.67. GMAC Single Collision Frames Register 64.8.68. GMAC Multiple Collision Frames Register 64.8.69. GMAC Excessive Collisions Register 64.8.70. GMAC Late Collisions Register 64.8.71. GMAC Deferred Transmission Frames Register 64.8.72. GMAC Carrier Sense Errors Register 64.8.73. GMAC Octets Received Low Register 64.8.74. GMAC Octets Received High Register 64.8.75. GMAC Frames Received Register 64.8.76. GMAC Broadcast Frames Received Register 64.8.77. GMAC Multicast Frames Received Register 64.8.78. GMAC Pause Frames Received Register 64.8.79. GMAC 64 Byte Frames Received Register 64.8.80. GMAC 65 to 127 Byte Frames Received Register 64.8.81. GMAC 128 to 255 Byte Frames Received Register 64.8.82. GMAC 256 to 511 Byte Frames Received Register 64.8.83. GMAC 512 to 1023 Byte Frames Received Register 64.8.84. GMAC 1024 to 1518 Byte Frames Received Register 64.8.85. GMAC 1519 to Maximum Byte Frames Received Register 64.8.86. GMAC Undersized Frames Received Register 64.8.87. GMAC Oversized Frames Received Register 64.8.88. GMAC Jabbers Received Register 64.8.89. GMAC Frame Check Sequence Errors Register 64.8.90. GMAC Length Field Frame Errors Register 64.8.91. GMAC Receive Symbol Errors Register 64.8.92. GMAC Alignment Errors Register 64.8.93. GMAC Receive Resource Errors Register 64.8.94. GMAC Receive Overruns Register 64.8.95. GMAC IP Header Checksum Errors Register 64.8.96. GMAC TCP Checksum Errors Register 64.8.97. GMAC UDP Checksum Errors Register 64.8.98. GMAC_FLRXPCR 64.8.99. GMAC 1588 Timer Increment Sub-nanoseconds Register 64.8.100. GMAC 1588 Timer Seconds High Register 64.8.101. GMAC 1588 Timer Seconds Low Register 64.8.102. GMAC 1588 Timer Nanoseconds Register 64.8.103. GMAC 1588 Timer Adjust Register 64.8.104. GMAC 1588 Timer Increment Register 64.8.105. GMAC PTP Event Frame Transmitted Seconds Low Register 64.8.106. GMAC PTP Event Frame Transmitted Nanoseconds Register 64.8.107. GMAC PTP Event Frame Received Seconds Low Register 64.8.108. GMAC PTP Event Frame Received Nanoseconds Register 64.8.109. GMAC PTP Peer Event Frame Transmitted Seconds Low Register 64.8.110. GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 64.8.111. GMAC PTP Peer Event Frame Received Seconds Low Register 64.8.112. GMAC PTP Peer Event Frame Received Nanoseconds Register 64.8.113. GMAC_TXPQUANT1 64.8.114. GMAC_TXPQUANT2 64.8.115. GMAC_TXPQUANT3 64.8.116. GMAC Received LPI Transitions 64.8.117. GMAC Received LPI Time 64.8.118. GMAC Transmit LPI Transitions 64.8.119. GMAC Transmit LPI Time 64.8.120. GMAC_QOS_CFG0 64.8.121. GMAC_QOS_CFG1 64.8.122. GMAC Interrupt Status Register Priority Queue x 64.8.123. GMAC Transmit Buffer Queue Base Address Register Priority Queue x 64.8.124. GMAC Receive Buffer Queue Base Address Register Priority Queue x 64.8.125. GMAC Receive Buffer Size Register Priority Queue x 64.8.126. GMAC Credit-Based Shaping Control Register 64.8.127. GMAC Credit-Based Shaping IdleSlope Register for Queue A 64.8.128. GMAC Credit-Based Shaping IdleSlope Register for Queue B 64.8.129. GMAC_TQUBA 64.8.130. GMAC_TXBDCTRL 64.8.131. GMAC_RXBDCTRL 64.8.132. GMAC_RQUBA 64.8.133. GMAC Screening Type 1 Register x Priority Queue 64.8.134. GMAC Screening Type 2 Register x Priority Queue 64.8.135. GMAC_TSCTL 64.8.136. GMAC_TQBWRL0 64.8.137. GMAC_TQBWRL1 64.8.138. GMAC_TQSA 64.8.139. GMAC Interrupt Enable Register Priority Queue x 64.8.140. GMAC Interrupt Disable Register Priority Queue x 64.8.141. GMAC Interrupt Mask Register Priority Queue x 64.8.142. GMAC Screening Type 2 EtherType Register x 64.8.143. GMAC Screening Type 2 Compare Word 0 Register x 64.8.144. GMAC Screening Type 2 Compare Word 1 Register x 65. Flexible Serial Communication Controller (FLEXCOM) 65.1. Description 65.2. Embedded Characteristics 65.2.1. USART/UART Characteristics 65.2.2. SPI Characteristics 65.2.3. TWI/SMBus Characteristics 65.3. Block Diagram 65.4. I/O Lines Description 65.5. Product Dependencies 65.5.1. I/O Lines 65.5.2. Power Management 65.5.3. Interrupt Sources 65.6. Register Accesses 65.7. USART Functional Description 65.7.1. Baud Rate Generator 65.7.1.1. Baud Rate in Asynchronous Mode 65.7.1.1.1. Baud Rate Calculation Example 65.7.1.2. Fractional Baud Rate in Asynchronous Mode 65.7.1.3. Baud Rate in Synchronous Mode 65.7.1.4. Baud Rate in ISO 7816 Mode 65.7.2. Receiver and Transmitter Control 65.7.3. Synchronous and Asynchronous Modes 65.7.3.1. Transmitter Operations 65.7.3.2. Manchester Encoder 65.7.3.2.1. Drift Compensation 65.7.3.3. Asynchronous Receiver 65.7.3.4. Manchester Decoder 65.7.3.5. Radio Interface: Manchester Encoded USART Application 65.7.3.6. Synchronous Receiver 65.7.3.7. Receiver Operations 65.7.3.8. Parity 65.7.3.9. Multidrop Mode 65.7.3.10. Transmitter Timeguard 65.7.3.11. Receiver Timeout 65.7.3.12. Framing Error 65.7.3.13. Transmit Break 65.7.3.14. Receive Break 65.7.3.15. Hardware Handshaking 65.7.4. ISO7816 Mode 65.7.4.1. ISO7816 Mode Overview 65.7.4.2. Protocol T = 0 65.7.4.2.1. Receive Error Counter 65.7.4.2.2. Receive NACK Inhibit 65.7.4.2.3. Transmit Character Repetition 65.7.4.2.4. Disable Successive Receive NACK 65.7.4.3. Protocol T = 1 65.7.5. IrDA Mode 65.7.5.1. IrDA Modulation 65.7.5.2. IrDA Baud Rate 65.7.5.3. IrDA Demodulator 65.7.6. RS485 Mode 65.7.7. USART Comparison Function on Received Character 65.7.8. USART Asynchronous and Partial Wakeup 65.7.9. LIN Mode 65.7.9.1. Modes of Operation 65.7.9.2. Baud Rate Configuration 65.7.9.3. Receiver and Transmitter Control 65.7.9.4. Character Transmission 65.7.9.5. Character Reception 65.7.9.6. Header Transmission (Host Node Configuration) 65.7.9.7. Header Reception (Client Node Configuration) 65.7.9.8. Client Node Synchronization 65.7.9.9. Identifier Parity 65.7.9.10. Node Action 65.7.9.11. Response Data Length 65.7.9.12. Checksum 65.7.9.13. Frame Slot Mode 65.7.9.14. LIN Errors 65.7.9.14.1. Bit Error 65.7.9.14.2. Inconsistent Synch Field Error 65.7.9.14.3. Identifier Parity Error 65.7.9.14.4. Checksum Error 65.7.9.14.5. Client Not Responding Error 65.7.9.14.6. Synch Tolerance Error 65.7.9.14.7. Header Timeout Error 65.7.9.15. LIN Frame Handling 65.7.9.15.1. Host Node Configuration 65.7.9.15.2. Client Node Configuration 65.7.9.16. LIN Frame Handling with the DMAC 65.7.9.16.1. Host Node Configuration 65.7.9.16.2. Client Node Configuration 65.7.9.17. Wakeup Request 65.7.9.18. Bus Idle Timeout 65.7.10. Test Modes 65.7.10.1. Normal Mode 65.7.10.2. Automatic Echo Mode 65.7.10.3. Local Loopback Mode 65.7.10.4. Remote Loopback Mode 65.7.11. USART FIFOs 65.7.11.1. Overview 65.7.11.2. Sending Data with FIFO Enabled 65.7.11.3. Receiving Data with FIFO Enabled 65.7.11.4. Clearing/Flushing FIFOs 65.7.11.5. TXEMPTY, TXRDY and RXRDY Behavior 65.7.11.6. FIFO Single Data Access 65.7.11.6.1. DMAC 65.7.11.7. FIFO Multiple Data Access 65.7.11.7.1. TXRDY and RXRDY Configuration 65.7.11.7.2. DMAC 65.7.11.8. Transmit FIFO Lock 65.7.11.9. FIFO Pointer Error 65.7.11.10. FIFO Thresholds 65.7.11.11. FIFO Flags 65.7.12. 16-bit Data Protocol Support 65.7.13. USART Register Write Protection 65.8. SPI Functional Description 65.8.1. Modes of Operation 65.8.2. Data Transfer 65.8.3. Host Mode Operations 65.8.3.1. Host Mode Block Diagram 65.8.3.2. Host Mode Flowchart 65.8.3.3. Clock Generation 65.8.3.4. Transfer Delays 65.8.3.5. Peripheral Selection 65.8.3.6. SPI Direct Access Memory Controller (DMAC) 65.8.3.7. Peripheral Chip Select Decoding 65.8.3.8. Peripheral Deselection without DMA 65.8.3.9. Peripheral Deselection with DMA 65.8.3.10. Mode Fault Detection 65.8.4. SPI Client Mode 65.8.5. SPI Comparison Function on Received Character 65.8.6. SPI Asynchronous and Partial Wake-up 65.8.7. SPI FIFOs 65.8.7.1. Overview 65.8.7.2. Sending Data with FIFO Enabled 65.8.7.3. Receiving Data with FIFO Enabled 65.8.7.4. Clearing/Flushing FIFOs 65.8.7.5. TXEMPTY, TDRE and RDRF Behavior 65.8.7.6. SPI Single Data Access 65.8.7.6.1. DMAC 65.8.7.7. SPI Multiple Data Access 65.8.7.7.1. TDRE and RDRF Configuration 65.8.7.7.2. DMAC 65.8.7.8. FIFO Pointer Error 65.8.7.9. FIFO Thresholds 65.8.7.10. FIFO Flags 65.8.8. SPI Register Write Protection 65.8.9. Local Loopback Test Mode 65.9. TWI Functional Description 65.9.1. Transfer Format 65.9.1.1. Digital Filter 65.9.2. Modes of Operation 65.9.3. Host Mode 65.9.3.1. Definition 65.9.3.2. Programming Host Mode 65.9.3.3. Transfer Speed/Bit Rate 65.9.3.4. Host Transmitter Mode 65.9.3.5. Host Receiver Mode 65.9.3.6. Internal Address 65.9.3.6.1. 7-bit Client Addressing 65.9.3.6.2. 10-bit Client Addressing 65.9.3.7. Repeated Start 65.9.3.8. Bus Clear Command 65.9.3.9. SMBus Mode 65.9.3.9.1. Packet Error Checking 65.9.3.9.2. Timeouts 65.9.3.10. SMBus Quick Command (Host Mode Only) 65.9.3.11. TWI High-Speed Host 65.9.3.11.1. Read-Write Operation 65.9.3.11.2. SCL Rising Time Control 65.9.3.11.3. TWI High-Speed Mode Usage 65.9.3.12. Alternative Command 65.9.3.13. Handling Errors in Alternative Command 65.9.3.14. Read/Write Flowcharts 65.9.4. Multi-Host Mode 65.9.4.1. Definition 65.9.4.2. Different Multi-Host Modes 65.9.4.2.1. TWI as Host Only 65.9.4.2.2. TWI as Host or Client 65.9.5. Client Mode 65.9.5.1. Definition 65.9.5.2. Programming Client Mode 65.9.5.3. Receiving Data 65.9.5.3.1. Read Sequence 65.9.5.3.2. Write Sequence 65.9.5.3.3. Clock Stretching Sequence 65.9.5.3.4. General Call 65.9.5.4. Data Transfer 65.9.5.4.1. Read Operation 65.9.5.4.2. Write Operation 65.9.5.4.3. General Call 65.9.5.4.4. Clock Stretching 65.9.5.4.4.1. — Clock Stretching in Read Mode 65.9.5.4.4.2. — Clock Stretching in Write Mode 65.9.5.4.5. Reversal after a Repeated Start 65.9.5.4.5.1. — Reversal of Read to Write 65.9.5.4.5.2. — Reversal of Write to Read 65.9.5.4.6. SMBus Mode 65.9.5.4.6.1. — Packet Error Checking 65.9.5.4.6.2. — Timeouts 65.9.5.5. High-Speed Client Mode 65.9.5.5.1. Read/Write Operation 65.9.5.5.2. Usage 65.9.5.6. Alternative Command 65.9.5.7. TWI Asynchronous and Partial Wakeup 65.9.5.8. Client Read/Write Flowcharts 65.9.6. TWI FIFOs 65.9.6.1. Overview 65.9.6.2. Sending Data with FIFO Enabled 65.9.6.3. Receiving Data with FIFO Enabled 65.9.6.4. Sending/Receiving with FIFO Enabled in Client Mode 65.9.6.5. Clearing/Flushing FIFOs 65.9.6.6. TXRDY and RXRDY Behavior 65.9.6.7. TWI Single Data Access 65.9.6.8. TWI Multiple Data Access 65.9.6.8.1. TXRDY and RXRDY Configuration 65.9.6.8.2. DMAC 65.9.6.9. Transmit FIFO Lock 65.9.6.10. FIFO Pointer Error 65.9.6.11. FIFO Thresholds 65.9.6.12. FIFO Flags 65.9.7. TWI Comparison Function on Received Character 65.9.8. Sniffer Mode 65.9.9. TWI Register Write Protection 65.10. Register Summary 65.10.1. FLEXCOM Mode Register 65.10.2. FLEXCOM Receive Holding Register 65.10.3. FLEXCOM Transmit Holding Register 65.10.4. USART Control Register 65.10.5. USART Mode Register 65.10.6. USART Interrupt Enable Register 65.10.7. USART Interrupt Enable Register (LIN_MODE) 65.10.8. USART Interrupt Disable Register 65.10.9. USART Interrupt Disable Register (LIN_MODE) 65.10.10. USART Interrupt Mask Register 65.10.11. USART Interrupt Mask Register (LIN_MODE) 65.10.12. USART Channel Status Register 65.10.13. USART Channel Status Register (LIN_MODE) 65.10.14. USART Receive Holding Register 65.10.15. USART Receive Holding Register (FIFO Multi Data) 65.10.16. USART Transmit Holding Register 65.10.17. USART Transmit Holding Register (FIFO Multi Data) 65.10.18. USART Baud Rate Generator Register 65.10.19. USART Receiver Timeout Register 65.10.20. USART Transmitter Timeguard Register 65.10.21. USART FI DI RATIO Register 65.10.22. USART Number of Errors Register 65.10.23. USART IrDA FILTER Register 65.10.24. USART Manchester Configuration Register 65.10.25. USART LIN Mode Register 65.10.26. USART LIN Identifier Register 65.10.27. USART LIN Baud Rate Register 65.10.28. USART Comparison Register 65.10.29. USART FIFO Mode Register 65.10.30. USART FIFO Level Register 65.10.31. USART FIFO Interrupt Enable Register 65.10.32. USART FIFO Interrupt Disable Register 65.10.33. USART FIFO Interrupt Mask Register 65.10.34. USART FIFO Event Status Register 65.10.35. USART Write Protection Mode Register 65.10.36. USART Write Protection Status Register 65.10.37. SPI Control Register 65.10.38. SPI Mode Register 65.10.39. SPI Receive Data Register 65.10.40. SPI Receive Data Register (FIFO Multiple Data, 8-bit) 65.10.41. SPI Receive Data Register (FIFO Multiple Data, 16-bit) 65.10.42. SPI Transmit Data Register 65.10.43. SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit) 65.10.44. SPI Status Register 65.10.45. SPI Interrupt Enable Register 65.10.46. SPI Interrupt Disable Register 65.10.47. SPI Interrupt Mask Register 65.10.48. SPI Chip Select Register 65.10.49. SPI FIFO Mode Register 65.10.50. SPI FIFO Level Register 65.10.51. SPI Comparison Register 65.10.52. SPI Write Protection Mode Register 65.10.53. SPI Write Protection Status Register 65.10.54. TWI Control Register 65.10.55. TWI Control Register (FIFO_ENABLED) 65.10.56. TWI Host Mode Register 65.10.57. TWI Client Mode Register 65.10.58. TWI Internal Address Register 65.10.59. TWI Clock Waveform Generator Register 65.10.60. TWI Status Register 65.10.61. TWI Status Register (FIFO ENABLED) 65.10.62. TWI Interrupt Enable Register 65.10.63. TWI Interrupt Disable Register 65.10.64. TWI Interrupt Mask Register 65.10.65. TWI Receive Holding Register 65.10.66. TWI Receive Holding Register (FIFO Enabled) 65.10.67. TWI Transmit Holding Register 65.10.68. TWI Transmit Holding Register (FIFO Enabled) 65.10.69. TWI SMBus Timing Register 65.10.70. FLEX_TWI_HSR 65.10.71. TWI Alternative Command Register 65.10.72. TWI Filter Register 65.10.73. FLEX_TWI_HSCWGR 65.10.74. TWI Matching Register 65.10.75. TWI FIFO Mode Register 65.10.76. TWI FIFO Level Register 65.10.77. TWI FIFO Status Register 65.10.78. TWI FIFO Interrupt Enable Register 65.10.79. TWI FIFO Interrupt Disable Register 65.10.80. TWI FIFO Interrupt Mask Register 65.10.81. TWI Write Protection Mode Register 65.10.82. TWI Write Protection Status Register 66. Quad Serial Peripheral Interface (QSPI) 66.1. Description 66.2. Embedded Characteristics 66.3. Block Diagram 66.4. Signal Description 66.5. Product Dependencies 66.5.1. I/O Lines 66.5.2. Power Management 66.5.3. Interrupt Sources 66.5.4. Direct Memory Access Controller (DMA) 66.6. Functional Description 66.6.1. Register Synchronization 66.6.2. Updating the QSPI Configuration 66.6.2.1. Changing QSPI_IFR Configuration (QSPI_MR.SMM = 1) 66.6.3. Serial Clock Phase and Polarity 66.6.4. Transfer Delays 66.6.5. DLL 66.6.6. DQS Delay 66.6.7. Pad Calibration 66.6.8. Refresh Sequence 66.6.8.1. Automatic Refresh 66.6.8.2. On-Demand Refresh 66.6.9. QSPI SPI Mode 66.6.9.1. SPI Mode Operations 66.6.9.2. SPI Mode Block Diagram 66.6.9.3. SPI Mode Flow Diagram 66.6.9.4. Peripheral Deselection without DMA 66.6.9.5. Peripheral Deselection with DMA 66.6.10. QSPI Serial Memory Mode 66.6.10.1. Initialization 66.6.10.2. Suspend 66.6.10.3. Instruction Frame 66.6.10.4. Instruction Frame Transmission 66.6.10.4.1. Memory Registers/Commands Access 66.6.10.4.2. Memory Array Access 66.6.10.5. Write Memory Transfer 66.6.10.6. Read Memory Transfer 66.6.10.7. Continuous Read Mode 66.6.10.8. Instruction Frame Transmission Examples 66.6.10.9. Twin-Quad Mode 66.6.10.10. Endianness 66.6.10.11. Octal DDR Mode 66.6.10.12. HyperFlash Mode 66.6.10.13. Time-out 66.6.11. Scrambling/Unscrambling Function 66.6.11.1. Clearing Scrambling Keys on a Tamper Event 66.6.12. Register Write Protection 66.7. Register Summary 66.7.1. QSPI Control Register 66.7.2. QSPI Mode Register 66.7.3. QSPI Receive Data Register 66.7.4. QSPI Transmit Data Register 66.7.5. QSPI Interrupt Status Register 66.7.6. QSPI Interrupt Enable Register 66.7.7. QSPI Interrupt Disable Register 66.7.8. QSPI Interrupt Mask Register 66.7.9. QSPI Serial Clock Register 66.7.10. QSPI Status Register 66.7.11. QSPI Instruction Address Register 66.7.12. QSPI Write Instruction Code Register 66.7.13. QSPI Instruction Frame Register 66.7.14. QSPI Read Instruction Code Register 66.7.15. QSPI Scrambling Mode Register 66.7.16. QSPI Scrambling Key Register 66.7.17. QSPI Refresh Register 66.7.18. QSPI Write Access Counter Register 66.7.19. QSPI DLL Configuration Register 66.7.20. QSPI Pad Calibration Configuration Register 66.7.21. QSPI Pad Calibration Bypass Register 66.7.22. QSPI Timeout Register 66.7.23. QSPI Write Protection Mode Register 66.7.24. QSPI Write Protection Status Register 67. Secure Digital MultiMedia Card Controller (SDMMC) 67.1. Description 67.2. Embedded Characteristics 67.3. Embedded Features for SDMMC0/1/2 67.4. Reference Documents 67.5. Block Diagram 67.6. Application Block Diagram 67.7. Pin Name List 67.8. Product Dependencies 67.8.1. I/O Lines 67.8.2. Power Management 67.8.3. Interrupt Sources 67.9. SD/SDIO Operating Mode 67.10. e.MMC Operating Mode 67.10.1. Boot Operation Mode 67.10.1.1. Boot Procedure, Processor Mode 67.10.1.2. Boot Procedure, SDMA Mode 67.10.1.3. Boot Procedure, ADMA Mode 67.11. SDR104 / HS200 Tuning 67.11.1. DLL and Sampling Point 67.11.2. Retuning Method 67.11.2.1. SDMMC Tuning Sequence 67.12. I/O Calibration 67.13. e.MMC HS400 Timing Mode Selection 67.13.1. Enhanced Strobe Mode Disabled 67.13.2. Enhanced Strobe Mode Enabled 67.14. Register Summary 67.14.1. SDMMC SDMA System Address / Argument 2 Register 67.14.2. SDMMC Block Size Register 67.14.3. SDMMC Block Count Register 67.14.4. SDMMC Argument 1 Register 67.14.5. SDMMC Transfer Mode Register 67.14.6. SDMMC Command Register 67.14.7. SDMMC Response Register x 67.14.8. SDMMC Buffer Data Port Register 67.14.9. SDMMC Present State Register 67.14.10. SDMMC Host Control 1 Register (SD_SDIO) 67.14.11. SDMMC Host Control 1 Register (e.MMC) 67.14.12. SDMMC Power Control Register 67.14.13. SDMMC Block Gap Control Register (SD_SDIO) 67.14.14. SDMMC Block Gap Control Register (e.MMC) 67.14.15. SDMMC Wakeup Control Register (SD_SDIO) 67.14.16. SDMMC Clock Control Register 67.14.17. SDMMC Timeout Control Register 67.14.18. SDMMC Software Reset Register 67.14.19. SDMMC Normal Interrupt Status Register (SD_SDIO) 67.14.20. SDMMC Normal Interrupt Status Register (e.MMC) 67.14.21. SDMMC Error Interrupt Status Register (SD_SDIO) 67.14.22. SDMMC Error Interrupt Status Register (e.MMC) 67.14.23. SDMMC Normal Interrupt Status Enable Register (SD_SDIO) 67.14.24. SDMMC Normal Interrupt Status Enable Register (e.MMC) 67.14.25. SDMMC Error Interrupt Status Enable Register (SD_SDIO) 67.14.26. SDMMC Error Interrupt Status Enable Register (e.MMC) 67.14.27. SDMMC Normal Interrupt Signal Enable Register (SD_SDIO) 67.14.28. SDMMC Normal Interrupt Signal Enable Register (e.MMC) 67.14.29. SDMMC Error Interrupt Signal Enable Register (SD_SDIO) 67.14.30. SDMMC Error Interrupt Signal Enable Register (e.MMC) 67.14.31. SDMMC Auto CMD Error Status Register 67.14.32. SDMMC Host Control 2 Register (SD_SDIO) 67.14.33. SDMMC Host Control 2 Register (e.MMC) 67.14.34. SDMMC Capabilities 0 Register 67.14.35. SDMMC Capabilities 1 Register 67.14.36. SDMMC Maximum Current Capabilities Register 67.14.37. SDMMC Force Event Register for Auto CMD Error Status 67.14.38. SDMMC Force Event Register for Error Interrupt Status 67.14.39. SDMMC ADMA Error Status Register 67.14.40. SDMMC ADMA System Address Register 0 67.14.41. SDMMC Preset Value Register 67.14.42. SDMMC Slot Interrupt Status Register 67.14.43. SDMMC Host Controller Version Register 67.14.44. SDMMC Additional Present State Register 67.14.45. SDMMC e.MMC Control 1 Register 67.14.46. SDMMC e.MMC Control 2 Register 67.14.47. SDMMC e.MMC Control 3 Register 67.14.48. SDMMC Debounce Register 67.14.49. SDMMC AHB Control Register 67.14.50. SDMMC Clock Control 2 Register 67.14.51. SDMMC Retuning Control 1 Register 67.14.52. SDMMC Retuning Control 2 Register 67.14.53. SDMMC Retuning Counter Value Register 67.14.54. SDMMC Retuning Interrupt Status Enable Register 67.14.55. SDMMC Retuning Interrupt Signal Enable Register 67.14.56. SDMMC Retuning Interrupt Status Register 67.14.57. SDMMC Retuning Status Slots Register 67.14.58. SDMMC Tuning Control Register 67.14.59. SDMMC Capabilities Control Register 67.14.60. SDMMC Debug Register 67.14.61. SDMMC Calibration Control Register 67.14.62. SDMMC Extended Preset Value Register 8 68. Controller Area Network (MCAN) 68.1. Description 68.2. Embedded Characteristics 68.3. Block Diagram 68.4. Product Dependencies 68.4.1. I/O Lines 68.4.2. Power Management 68.4.3. Interrupt Sources 68.4.4. Address Configuration 68.4.5. Timestamping 68.5. Functional Description 68.5.1. Operating Modes 68.5.1.1. Software Initialization 68.5.1.2. Normal Operation 68.5.1.3. CAN FD Operation 68.5.1.4. Transmitter Delay Compensation 68.5.1.4.1. Description 68.5.1.4.2. Transmitter Delay Measurement 68.5.1.5. Restricted Operation Mode 68.5.1.6. Bus Monitoring Mode 68.5.1.7. Disabled Automatic Retransmission 68.5.1.7.1. Frame Transmission in DAR Mode 68.5.1.8. Power-down (Sleep Mode) 68.5.1.9. Test Modes 68.5.1.9.1. External Loop Back Mode 68.5.1.9.2. Internal Loop Back Mode 68.5.2. Timestamp Generation 68.5.3. Timeout Counter 68.5.4. Rx Handling 68.5.4.1. Acceptance Filtering 68.5.4.1.1. Range Filter 68.5.4.1.2. Filter for Specific IDs 68.5.4.1.3. Classic Bit Mask Filter 68.5.4.1.4. Standard Message ID Filtering 68.5.4.1.4.1. Extended Message ID Filtering 68.5.4.2. Rx FIFOs 68.5.4.2.1. Rx FIFO Blocking Mode 68.5.4.2.2. Rx FIFO Overwrite Mode 68.5.4.3. Dedicated Rx Buffers 68.5.4.3.1. Rx Buffer Handling 68.5.4.4. Debug on CAN Support 68.5.4.4.1. Filtering for Debug Messages 68.5.4.4.2. Debug Message Handling 68.5.5. Tx Handling 68.5.5.1. Transmit Pause 68.5.5.2. Dedicated Tx Buffers 68.5.5.3. Tx FIFO 68.5.5.4. Tx Queue 68.5.5.5. Mixed Dedicated Tx Buffers / Tx FIFO 68.5.5.6. Mixed Dedicated Tx Buffers / Tx Queue 68.5.5.7. Transmit Cancellation 68.5.5.8. Tx Event Handling 68.5.6. FIFO Acknowledge Handling 68.5.7. Message RAM 68.5.7.1. Message RAM Configuration 68.5.7.2. Rx Buffer and FIFO Element 68.5.7.3. Tx Buffer Element 68.5.7.4. Tx Event FIFO Element 68.5.7.5. Standard Message ID Filter Element 68.5.7.6. Extended Message ID Filter Element 68.5.8. Hardware Reset Description 68.5.9. Access to Reserved Register Addresses 68.6. Register Summary 68.6.1. MCAN Endian Register 68.6.2. MCAN Data Bit Timing and Prescaler Register 68.6.3. MCAN Test Register 68.6.4. MCAN RAM Watchdog Register 68.6.5. MCAN CC Control Register 68.6.6. MCAN Nominal Bit Timing and Prescaler Register 68.6.7. MCAN Timestamp Counter Configuration Register 68.6.8. MCAN Timestamp Counter Value Register 68.6.9. MCAN Timeout Counter Configuration Register 68.6.10. MCAN Timeout Counter Value Register 68.6.11. MCAN Error Counter Register 68.6.12. MCAN Protocol Status Register 68.6.13. MCAN Transmitter Delay Compensation Register 68.6.14. MCAN Interrupt Register 68.6.15. MCAN Interrupt Enable Register