Master Clock Timing

The I²C module clock is generated by module hardware in Master mode. The I2CxCLK register provides the clock source for the module, which can be selected from several peripherals. Master clock timing is controlled by the Fast Mode Enable (FME) bit of the I2CxCON2 register. The FME bit controls the number of times the SCL pin is sampled before the master hardware drives it.

Important: Note that the I²C clock is not the same as the SCL, rather it is used to time the SCL output.

The clock source selected by I2CxCLK, in combination with the FME bit, is used by master hardware to time the SCL signal. For example, if the Medium Frequency Internal Oscillator (MFINTOSC), which generates a 500 kHz output, is selected as the I²C clock source, the SCL frequency would not be 500 kHz. The MFINTOSC signal would be divided by either 4 or 5, depending on the value of the FME bit (see equations below).

When the FME bit is cleared, one SCL period (T_SCL) consists of five clock periods of the I²C clock input source selected by the I2CxCLK register (see figure below). The first clock period is used to drive SCL low, and the second clock period samples SCL to ensure it is in fact low. The third clock period releases SCL high, and the fourth and fifth clock periods sample the SCL to detect if the SCL pin is indeed high or if the slave is stretching the clock.

If the slave is stretching the clock, module hardware waits, checking each successive I²C clock period until the hardware detects a high level on SCL. Once the high level is detected, hardware uses the next two successive I²C clock periods to verify the SCL is high.

Figure 1. SCL Frequency Example (FME = 0)

When FME = 0

fSCL=fI2CCLK5

Example:

I2CxCLK = MFINTOSC (500 kHz)
FME = 0

fSCL=500⁢kHz5=100⁢ kHz

Figure 2. I²C SCL Timing (FME = 0)

When the FME bit is set, one SCL period (T_SCL) consists of four clock periods of the I²C clock input source selected by the I2CxCLK register (see figure below). The first clock period drives SCL low, and the second clock period samples SCL to ensure it is low. The third clock period causes the master to release the SCL, driving SCL high. The fourth clock period samples SCL to determine whether it is high or being stretched by a slave. If the slave is stretching the clock, module hardware waits, checking each successive I²C clock period until the hardware detects a high level on SCL. Once the high level is detected, hardware uses the next successive I²C clock period to verify if the SCL is high.

Figure 3. SCL Frequency Example (FME = 1)

When FME = 1

fSCL=fI2CCLK4

Example:

I2CxCLK = MFINTOSC (500 kHz)
FME = 1

fSCL=500⁢kHz4=125⁢ ⁢kHz

Figure 4. I²C SCL Timing (FME = 1)