Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C Flag of the SREG. This operation effectively divides a signed value by two without changing its sign. The Carry Flag can be used to round the result.
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Operation: |
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Operands: |
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(i) |
ASR Rd |
0 ≤ d ≤ 31 |
PC ← PC + 1 |
16-bit Opcode:
| 1001 | 010d | dddd | 0101 |