Status Register (SREG) and Boolean Formula

H

Ρ3 + Rd3

Set if there was a borrow from bit 3; cleared otherwise.

S

N ⊕ V, for signed tests.

V

R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if there is a two’s complement overflow from the implied subtraction from zero; cleared otherwise. A two’s complement overflow will occur if and only if the contents of the Register after operation (Result) is $80.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C

R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0

Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C Flag will be set in all cases except when the contents of Register after operation is $00.

R (Result) equals Rd after the operation.

Example:

 sub r11,r0 ; Subtract r0 from r11
 brpl positive ; Branch if result positive
 neg r11 ; Take two’s complement of r11
positive: nop ; Branch destination (do nothing)

Words

1 (2 bytes)

Cycles

1