Status Register (SREG) and Boolean Formula

I	T	H	S	V	N	Z	C
–	–	–	–	–	–	⇔	⇔

C

R16

Set if bit 15 of the result before left shift is set; cleared otherwise.

Z

R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

fmuls r23,r22 ; Multiply signed r23 and r22 in (1.7) format, result in (1.15) format
mov w r23:r22,r1:r0 ; Copy result back in r23:r22