Status Register (SREG) and Boolean Formula

I T H S V N Z C
H

Rd3 • Rr3 + Rr3 • R3 + R3 • Rd3

Set if there was a carry from bit 3; cleared otherwise.

S
N ⊕ V, for signed tests.
V

Rd7 • Rr7 • R7 + Rd7Rr7 • R7

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N

R7

Set if MSB of the result is set; cleared otherwise.

Z

R7R6R5R4R3R2R1R0

Set if the result is $00; cleared otherwise.

C

Rd7 • Rr7 + Rr7 • R7 + R7 • Rd7

Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

             ; Add R1:R0 to R3:R2
add r2,r0    ; Add low byte
adc r3,r1    ; Add with carry high byte
Words
1 (2 bytes)
Cycles
1