DALI Control Device Mode

The DALI Control Device mode is configured using the following settings:

• Load the MODE<3:0> bits of U1CON0 with '0b1000', placing the UART into Control Device mode.
• Set the Transmit Enable Control (TXEN) bit of U1CON0 to allow transmission.
• Set the Receive Enable Control (RXEN) bit of U1CON0 to allow reception.
• Load the UART Parameter 1 Register (U1P1H:U1P1L) pair with the number of half-bit periods of Idle time between consecutive forward frame transmissions. In this case, the minimum value loaded should be 0x16, or 22 half-bit periods.
• Load the UART Parameter 2 Register (U1P2H:U1P2L) pair with the number of half-bit periods of idle time used to determine if the frame is a forward frame. If a frame is received before the half-bit delay expires, it is considered a backward frame. If reception occurs after the half-bit period delay expires, the frame is detected as a forward frame, and sets the Parity Error Interrupt Flag (PERIF) bit of the UART Error Interrupt Flag Register (U1ERRIR).
• Load the value used to achieve a 1200 baud rate into the UART Baud Rate Generator Register (U1BRGH:U1BRGL) pair.
• Configure the Transmit Polarity Control (TXPOL) bit of the UART Control Register 2 (U1CON2) to match the appropriate output polarity of the interface circuit.
• Configure the Receive Polarity Control (RXPOL) bit of U1CON2 to match the appropriate input polarity of the interface circuit.
• Load the value '0b10' into the Stop Bit Mode Control (STP<1:0>) bits of U1CON2 to ensure the frames contain two Stop bits as required by the DALI protocol.
• Load the RxyPPS register (PPS output) with the Tx pin selection code to map the Tx output to the desired pin.
• Configure the U1RXPPS register to match the desired input pin.
• Clear the TRIS bit associated with the Tx output pin.
• Set the TRIS bit associated with the Rx input pin.
• Clear the ANSEL bit associated with the Rx input pin.
• Set the Serial Port Enable (ON) bit of U1CON1.

A forward frame is initialized by writing the address byte into the UART Transmit Register (U1TXB). If there is no data residing in the Transmit Shift Register (TSR), the address byte is immediately transferred to the TSR, allowing the first data byte to be written into U1TXB. Once the TSR shifts out the address byte, the data in U1TXB is transferred into the TSR, setting the UART Transmit Interrupt Flag (U1TXIF) bit.

Once the U1TXIF is set, but before the Transmit Shift Register Empty Interrupt Flag (TXMTIF) bit of the U1ERRIR register is set, the next data byte must be loaded into U1TXB to ensure that each byte within the frame is transmitted without an interruption. The TXMTIF bit is set once the TSR has shifted out the last byte and there is no data in the U1TXB register, indicating the end of the frame. When TXMTIF is set, hardware holds the Tx output in the Idle state for the number of Stop bits selected by the STP<1:0> bits of U1CON2.

After the last Stop bit has been transmitted, the Tx output is held in the Idle state for the number of half-bit times found in the U1P1H:U1P1L register pair. Any writes to the U1TXB register that occur after TXMTIF has set but before the U1P1 wait time expires are held in U1TXB. Once the wait time expires, the data is immediately transmitted. If a backward frame is received during the wait time, any data written into U1TXB will be held until the complete reception of the backward frame plus the additional U1P1 wait time.

Once the two Stop bits of a backward frame have been received, the U1P1 wait timer resets and restarts its timing function. Any data pending in the TSR will be transmitted once the wait time elapses.

Forward frame data stored in the TSR and U1TXB can be replaced or deleted by setting the Transmit Buffer Empty Status (TXBE) bit of the UART FIFO Status register (U1FIFO). Setting TXBE flushes any data left in both the TSR and the U1TXB registers. It is important to note that the TXBE bit can only be cleared by hardware, and is clear whenever there is data in either the TSR or U1TXB.

It is important to note that backward frames are automatically received, and may or may not arrive within the allowed time window. If the backward frame arrives outside of the time window and collides with a forward frame, the Transmit Collision Interrupt Flag (TXCIF) bit of the U1ERRIR register is set. If the backward frame arrives outside of the time window and no collision occurs, the module continues normal operation. TXCIF will also be set when a received bit is missing the half-bit transition.