DALI Control Gear Mode

The DALI Control Gear mode is configured using the following settings:

• Load the MODE<3:0> bits of U1CON0 with '0b1001', placing the UART into Control Gear mode.
• Set the Transmit Enable Control (TXEN) bit of U1CON0 to allow transmission.
• Set the Receive Enable Control (RXEN) bit of U1CON0 to allow reception.
• Load the UART Parameter 1 Register (U1P1H:U1P1L) pair with the number of half-bit periods of Idle time between the reception of forward frame and the transmission of a backward frame. The allowable time frame is between 5.5 ms and 10.5 ms, so loading a value of 0x16 (22 half-bit periods or 9.17 ms) will meet the timing requirements.
• Load the UART Parameter 2 Register (U1P2H:U1P2L) pair with the number of half-bit periods of Idle time used to determine if the frame is a forward frame. If a frame is received before the half-bit delay expires, it is considered a backward frame. If reception occurs after the half-bit period delay, the frame is detected as a forward frame, and sets the Parity Error Interrupt Flag (PERIF) bit of the UART Error Interrupt Flag Register (U1ERRIR).
• Load the value used to achieve a 1200 baud rate into the UART Baud Rate Generator Register (U1BRGH:U1BRGL) pair.
• Configure the Transmit Polarity Control (TXPOL) bit of the UART Control Register 2 (U1CON2) to match the appropriate output polarity of the interface circuit.
• Configure the Receive Polarity Control (RXPOL) bit of U1CON2 to match the appropriate input polarity of the interface circuit.
• Load the value '0b10' into the Stop Bit Mode Control (STP<1:0>) bits of U1CON2 to ensure the frames contain two Stop bits as required by the DALI protocol.
• Load the RxyPPS register (PPS output) with the Tx pin selection code to map the Tx output to the desired pin.
• Configure the U1RXPPS register to match the desired input pin.
• Clear the TRIS bit associated with the Tx output pin.
• Set the TRIS bit associated with the Rx input pin.
• Clear the ANSEL bit associated with the Rx input pin.
• Set the Serial Port Enable (ON) bit of U1CON1.

When the UART is set into Control Gear mode and the serial port is enabled, the UART begins to monitor for a received forward frame. Frames that are received after the U1P2 wait time expires are detected as a forward frame and are stored in the receive FIFO; if a frame is received before the U1P2 wait time expires, the frame is detected as a backward frame and ignored since a control gear can only receive forward frames. Backward frames from other Control Gear are ignored.

Once the Control Gear receives the last Stop bit of the forward frame, hardware starts a timer to delay the backward frame response by the number of half-bit periods stored in the U1P1 register.

The data received in the forward frame is processed by the Control Gear's application software. If a response is required, the application software writes the backward frame into U1TXB. The frame is held for transmission until the wait time delay expires. If the response is written into U1TXB after the wait time delay expires, the TXMTIF bit is held low, and the response is held in U1TXB until a new forward frame is received and the wait time associated to that frame has expired. If the UART Receive Interrupt Flag (U1RXIF) bit is set before TXMTIF becomes set, it means that a new forward frame was received before the pending backward frame was sent. In this case, the pending backward frame may hold an incorrect response to the new forward frame, therefore, the pending backward frame can be deleted by setting the TXBE bit.