The XMEGA A1U Xplained Pro features a SRAM with latches for configuring the XMEGA in 2-PORT EBI mode. In this mode the address byte 0 and 1 is shared with data byte 0.
| Pin on XMEGA | SRAM |
|---|---|
| PJ0 | D0 (data) |
| PJ1 | D1 (data) |
| PJ2 | D2 (data) |
| PJ3 | D3 (data) |
| PJ4 | D4 (data) |
| PJ5 | D5 (data) |
| PJ6 | D6 (data) |
| PJ7 | D7 (data) |
| PJ0 through ALE1 latch | A0 (address) |
| PJ1 through ALE1 latch | A1 (address) |
| PJ2 through ALE1 latch | A2 (address) |
| PJ3 through ALE1 latch | A3 (address) |
| PJ4 through ALE1 latch | A4 (address) |
| PJ5 through ALE1 latch | A5 (address) |
| PJ6 through ALE1 latch | A6 (address) |
| PJ7 through ALE1 latch | A7 (address) |
| PJ0 through ALE2 latch | A8 (address) |
| PJ1 through ALE2 latch | A9 (address) |
| PJ2 through ALE2 latch | A10 (address) |
| PJ3 through ALE2 latch | A11 (address) |
| PJ4 through ALE2 latch | A12 (address) |
| PJ5 through ALE2 latch | A13 (address) |
| PJ6 through ALE2 latch | A14 (address) |
| PJ7 through ALE2 latch | A15 (address) |
| PH4 | A16 (address) |
| PH5 | A17 (address) |
| PK7 | A18 (address) |
| PH2 | ALE1 (Address Latch Enable 1) |
| PH3 | ALE2 (Address Latch Enable 2) |
| PH6 | CS |
| PH0 | WE |
| PH1 | RE |