The WayMaskX register allows a master connected to the L2 cache controller to specify which L2 cache ways can be evicted by master ‘X’ as specified in the WayMaskX register. Masters can still access memory cached in masked ways. At least one cache way must be enabled. It is recommended to set/clear bits in this register using atomic operations.
| Register Offset | 0x800 + (8 x Master ID) | |||
|---|---|---|---|---|
| Bits | Field Name | Attributes | Reset | Description |
| 0 | Way0 Mask | RW | 1 | Clearing this bit masks L2 Cache Way 0 |
| 1 | Way1 Mask | RW | 1 | Clearing this bit masks L2 Cache Way 1 |
| ... | ||||
| 15 | Way15 Mask | RW | 1 | Clearing this bit masks L2 Cache Way 15 |
| [63:16] | Reserved | RW | 1 | — |
The CPU Core Complex front port passes through an AXI to TileLink interface. This interface maps incoming transactions to the four internal TileLink IDs, which are referred in the above WayMaskX table. These IDs are not related to the incoming AXI transaction IDs. The allocation of the TileLink IDs is dependent on the number of outstanding AXI transactions, the arrival rate relative to the transaction completion cycle, and previous events. It is not possible to predict which internal ID will be allocated to each AXI transaction and therefore which set of way masks will apply to that AXI transaction. Hence, it is recommended that all four front port way masks are configured identically. See Table 1 for front port WayMaskX registers.