The Control register stores the current status of the channel. It can be used to claim a DMA channel, initiate a transfer, enable interrupts, and to check for the completion of a transfer. The following table defines the bit fields of the Control register.
| Register Offset | 0x000 + (0x1000 × Channel ID) | |||
|---|---|---|---|---|
| Bits | Field Name | Attributes | Reset | Description |
| 0 | claim | RW | 0 | Indicates that the channel is in use. Setting this bit clears all of the channel’s Next registers (NextConfig, NextBytes, NextDestination, and NextSource). This bit can only be cleared when run (CR bit 0) is low. |
| 1 | run | RW | 0 | Setting this bit starts a DMA transfer by copying the Next registers into their Exec counterparts |
| [13:2] | Reserved | — | 0 | — |
| 14 | doneIE | RW | 0 | Setting this bit will trigger the channel’s Done interrupt once a transfer is complete |
| 15 | errorIE | RW | 0 | Setting this bit will trigger the channel’s Error interrupt upon receiving a bus error |
| [28:16] | Reserved | — | 0 | — |
| 29 | Reserved | — | 0 | — |
| 30 | done | RW | 0 | Indicates that a transfer has completed since the channel was claimed |
| 31 | error | RW | 0 | Indicates that a transfer error has occurred since the channel was claimed |