The CSRs described in the following table implement the hardware performance monitoring scheme.
| CSR | Function |
|---|---|
| mcycle | Holds a count of the number of clock cycles executed by a Hart since some arbitrary time in the past. The arbitrary time is the time since power-up. |
| minstret | Holds a count of the number of instructions retired by a Hart since some arbitrary time in the past. The arbitrary time is the time since power-up. |
| mhpmevent3 and mhpmevent4 | Event Selectors: Selects the events as described in Table 2, and increments the corresponding mhpmcounter3 and mhpmcounter4 counters. The event selector register mhpmevent3 and mhpmevent4 are partitioned into two fields: event class and event mask as shown in Table 2. The lower 8 bits select an event class, and the upper bits form a mask of events in that class. The counter increments if the event corresponding to any set mask bit occurs. For example, if mhpmevent3 is set to 0x4200, mhpmcounter3 increments when either a load instruction or a conditional branch instruction retires. Note: In-flight and recently retired instructions may or may not be reflected when reading or writing the performance counters, or writing the event selectors.
|
| mhpmcounter3 and mhpmcounter4 | 40-bit event counters |
| Event Class | mhpmeventx[8:18] Bit Field Description Events |
|---|---|
| mhpmeventx[7:0] = 0: Instruction Commit Events | 8: Exception taken 9: Integer load instruction retired 10: Integer store instruction retired 11: Atomic memory operation retired 12: System instruction retired 13: Integer arithmetic instruction retired 14: Conditional branch retired 15: JAL instruction retired 16: JALR instruction retired 17: Integer multiplication instruction retired 18: Integer division instruction retired |
| mhpmeventx[7:0] = 1: Micro-architectural Events | 8: Load-use interlock 9: Long-latency interlock 10: CSR read interlock 11: Instruction cache/ITIM busy 12: Data cache/DTIM busy 13: Branch direction misprediction 14: Branch/jump target misprediction 15: Pipeline flush from CSR write 16: Pipeline flush from other event 17: Integer multiplication interlock |
| mhpmeventx[7:0] = 2: Memory System Events | 8: Instruction cache miss 9: Memory-mapped I/O access 10: Data cache write back 11: Instruction TLB miss 12: Data TLB miss Note: Only L1 cache performance monitoring is supported.
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