The following table lists the mhpmevent[7:0] register bit fields which correspond to BEU events that can be reported.
| Cause | Meaning |
|---|---|
| 0 | No Error |
| 1 | Reserved |
| 2 | Instruction cache or ITIM correctable ECC error |
| 3 | ITIM uncorrectable error |
| 4 | Reserved |
| 5 | Load or store TileLink bus error |
| 6 | Data cache correctable ECC error |
| 7 | Data cache uncorrectable ECC error |
When one of the events listed in Table 1 occurs, the BEU can record information about that event and can generate a global or local interrupt to the Hart. The enable register (Table 1) contains a mask of the events that can be recorded by the BEU. Each bit in the enable register corresponds to an event in Table 1. For example, if enable[3] is set, the BEU records uncorrectable ITIM errors.
The cause register indicates the event recorded most recently by the BEU. For example, a value of 3 indicates an uncorrectable ITIM error. The cause value 0 is reserved to indicate no error. The cause register is only written for events enabled in the enable register. The cause register is written when its current value is 0; that is, if multiple events occur, only the first one is latched, until software clears the cause register.
The value register holds the physical address that caused the event, or 0 if the address is unknown. The BEU writes to the value register whenever it writes the cause register. For example, when an event is enabled in the enable register and when the cause register contains 0.
The accrued register indicates all the events that occurred since the register was cleared by the software. Its format is the same as the enable register. The BEU sets bits in the accrued register whether or not they are enabled in the enable register.
The plic_interrupt register indicates the accrued events for which an interrupt must be generated via the PLIC. An interrupt is generated when any bit is set in accrued and plic_interrupt register. For example, when accrued and plic_interrupt is not 0.
The local_interrupt register indicates the accrued events for which an interrupt must be generated directly to the Hart. An interrupt is generated when any bit is set in both accrued and local_interrupt registers. For example, when accrued and local_interrupt is not 0.
The interrupt cause is 128; it does not have a bit in the
mie CSR, so it is always enabled; nor does it have a bit in the
mideleg CSR, so it cannot be delegated to a mode less privileged than
M-mode.