PMP Configuration Register (pmpcfg)

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pmpcfg0 and pmpcfg2 support eight PMP regions each as shown in Figure 1. These two registers hold the configurations for the 16 PMP regions. Each PMP region is referred as pmpicfg. In pmpicfg, i ranges from 0 to 15 (pmp0cfg, pmp1cfgpmp15cfg). PolarFire SoC supports RV64. For RV64, pmpcfg1 and pmpcfg3 are not used.

Figure 1. RV64 PMP Configuration CSR Layout

Figure 2 shows the layout of a pmpicfg register. The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively. When one of these bits is cleared, the corresponding access type is denied. The Address-Matching (A) field encodes the Address-Matching mode of the associated PMP address register. The Locking and Privilege mode (L) bit indicates that the PMP entry is locked.

Figure 2. PMP Configuration Register Format

The A field in a PMP entry's configuration register encodes the address-matching mode of the associated PMP address register. When A=0, this PMP entry is disabled and matches no addresses. Three address-matching modes are supported—Top of Range (TOR), naturally aligned four-byte regions (NA4), naturally aligned power-of-two regions (NAPOT) as listed in the following table.

Table 1. Encoding of A field in PMP Configuration Registers
Address Matching Name Description
0 OFF No region (disabled)
1 TOR Top of range
2 NA4 Naturally aligned four-byte region
3 NAPOT Naturally aligned power-of-two region, ≥ 8 bytes

NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range, as listed in Table 2.

Table 2. NAPOT Range Encoding
pmpaddr

(Binary)

pmpcfg.A Value Match Type and Size
aaaa…aaaa NA4 4-byte NAPOT range
aaaa…aaa0 NAPOT 8-byte NAPOT range
aaaa…aa01 NAPOT 16-byte NAPOT range
aaaa…a011 NAPOT 32-byte NAPOT range
... ... ...
aa01…1111 NAPOT 2XLEN-byte NAPOT range
a011…1111 NAPOT 2XLEN+1byte NAPOT range
0111…1111 NAPOT 2XLEN+2byte NAPOT range