The CPU Core Complex exposes 186 Global interrupt signals, these signals are connected to the PLIC. The mapping of these interrupt signals to their corresponding PLIC ID’s is provided in the following table.
| PLIC Interrupt ID Mapping | ||
|---|---|---|
| IRQ | Peripheral | Description |
| 1 | L2 Cache Controller | Signals when a metadata correction event occurs |
| 2 | L2 Cache Controller | Signals when an uncorrectable metadata event occurs |
| 3 | L2 Cache Controller | Signals when a data correction event occurs |
| 4 | L2 Cache Controller | Signals when an uncorrectable data event occurs |
| 5 | DMA Controller | Channel 0 Done |
| 6 | DMA Controller | Channel 0 Error |
| 7 | DMA Controller | Channel 1 Done |
| 8 | DMA Controller | Channel 1 Error |
| 9 | DMA Controller | Channel 2 Done |
| 10 | DMA Controller | Channel 2 Error |
| 11 | DMA Controller | Channel 3 Done |
| 12 | DMA Controller | Channel 3 Error |
| [181:13] | Off Core Complex | Connected to global_interrupts signal from MSS peripherals |
| 182 183 184 185 186 |
Bus Error Unit Hart0 Bus Error Unit Hart1 Bus Error Unit Hart2 Bus Error Unit Hart3 Bus Error Unit Hart4 |
Bus Error Unit described in Bus Error Unit (BEU). |
The Global interrupt signals are positive-level triggered. Any unused Global interrupts (inputs) must be tied to logic 0. In the PLIC, Global Interrupt ID 0 means “no interrupt”, therefore, Global interrupts[0] corresponds to PLIC Interrupt ID 1.