Each PLIC interrupt source can be assigned a priority by writing to its 32-bit memory-mapped priority register. A priority value of 0 is reserved to mean “never interrupt” and effectively disables the interrupt. Priority 1 is the lowest active priority, and priority 7 is the highest. Ties between global interrupts of the same priority are broken by the Interrupt ID; interrupts with the lowest ID have the highest effective priority. The priority register description is provided in the following table.
| Base Address = 0x0C00_0000 + 4 × Interrupt ID | ||||
|---|---|---|---|---|
| Bits | Field Name | Attributes | Reset | Description |
| [2:0] | Priority | WARL | X | Sets the priority for a given global interrupt. |
| [31:3] | Reserved | WIRI | X | — |