The per-Hart Trace and Debug Registers (TDRs) are listed in the following table.
| CSR Name | Description | Allowed Access Modes |
|---|---|---|
|
tselect tdata1 tdata2 tdata3 |
Trace and debug register select First field of selected TDR Second field of selected TDR Third field of selected TDR |
D, M D, M D, M D, M |
|
|
Debug control and status register Debug PC Debug scratch register |
D D D |
The dcsr, dpc, and
dscratch registers are accessible only in the Debug mode. The tselect
and tdata1–3 registers are accessible in the Debug mode or Machine mode.