External Bus Interfaces

The following six AMBA AXI4 compliant external ports enable the CPU Core Complex to access main memory and peripherals (see Figure 1).

• AXI 128 to DDR Controller
• D0 (Datapath0)
• D1 (Datapath1)
• F0 (FIFO0)
• F1 (FIFO1)
• NC (Non-Cached)

  To enable non-CPU masters to access the CPU Core Complex, there is an AMBA AXI4 compliant master bus port (S8 on the AXI Switch).