The following table lists the SDRAM interface signals.
| Signal Name | Direction | Description |
|---|---|---|
| CK | Output | Positive signal of differential clock pair forwarded to SDRAM. |
| CK_N | Output | Negative signal of differential clock pair forwarded to SDRAM. |
| RESET_N | Output | SDRAM reset. Supported only for DDR3 and DDR4. |
| A[15:0] | Output | Address bus. Sampled during the active, precharge, read, and write commands. Also provides the mode register value during MRS commands. Bus width for LPDDR3 is 10 bits, DDR3 is 16 bits, and DDR4 is 14 bits. |
| BA[2:0] | Output | Bank address. Sampled during active, precharge, read, and write commands to determine which bank the command is to be applied to. Supported only for DDR3 and DDR4. For DDR4, bus width is 2 bits. For DDR3, bus width is 3 bits. |
| BG[1:0] | Output | DDR bank group address for DDR4 only. |
| CS_N | Output | SDRAM Chip Select (CS). |
| CKE | Output | SDRAM clock enable. Held low during initialization to ensure SDRAM DQ and DQS outputs are in the hi-Z state. |
| RAS_N | Output | SDRAM row address strobe command. Supported only for DDR3 and DDR4. |
| CAS_N | Output | SDRAM column access strobe command. Supported only for DDR3 and DDR4. |
| WE_N | Output | SDRAM write enable command. Supported only for DDR3 and DDR4. |
| ODT | Output | On-die termination control. ODT is asserted during reads and writes according to the ODT activation settings in the standalone MSS Configurator. |
| PAR | Output | Command and address parity output. Supported only for DDR4. |
| ALERT_N | Input | Alert signaling command/address parity or write CRC error. Supported only for DDR4. |
| DQ | Bidirectional | SDRAM data bus. Supports 16-bit and 32-bit DDR SDRAM data buses. |
| DM/DM_N | Output | Write data mask. DM for DDR3/LPDDR3 and DM_N for DDR4. |
| DQS | Bidirectional | Strobes data into the SDRAM devices during writes and into the DDR subsystem during reads. |
| DQS_N | Bidirectional | Complimentary DQS. |