The MSS DDR Controller IP provides a high-performance interface to DDR3, DDR4, LPDDR3, and LPDDR4 SDRAM devices. The MSS DDR Controller accepts read and write requests via the AXI interfaces, and translates these requests to the command sequences required by DDR SDRAM devices. The MSS DDR Controller performs automatic initialization, refresh, and ZQ-calibration functions.
The following figure shows the functional blocks of the MSS DDR Controller.
Figure 1. MSS DDR Controller
