A GMII/MII is interfaced between each MAC and the FPGA fabric, to provide
flexibility to the user. It allows the following:
- Perform customized manipulation of data on-the-fly
- 8-bit parallel data lines are used for data transfer.
- In 10/100 Mbps mode txd[3:0] is used, txd[7:4] tied to Logic 0 while
transmission. rxd[3:0] is used, rxd[7:4] is tied to Logic 0 during reception of
data.
- In 1000 Mbps mode, all txd[7:0] and rxd[7:0] bits are used.