mstatus
)The mstatus
register tracks and controls the current
operating state of a Hart and tracks whether interrupts are enabled or not. Interrupts are
enabled by setting the MIE
bit and by enabling the required individual
interrupt in the mie
register described in the next section.
The mstatus
register description related to interrupts is
provided in Table 1. The mstatus
register also contains fields unrelated to interrupts. For a complete description of the
mstatus
register, see The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10.
Bits | Field Name | Attributes | Description |
---|---|---|---|
0 | Reserved | WPRI | — |
1 | SIE | RW | Supervisor Interrupt Enable |
2 | Reserved | WPRI | — |
3 | MIE | RW | Machine Interrupt Enable |
4 | Reserved | WPRI | — |
5 | SPIE | RW | Supervisor Previous Interrupt Enable |
6 | Reserved | WPRI | — |
7 | MPIE | RW | Machine Previous Interrupt Enable |
8 | SPP | RW | Supervisor Previous Privilege Mode |
[10:9] | Reserved | WPRI | — |
[12:11] | MPP | RW | Machine Previous Privilege Mode |