For improved performance, the CPU Core Complex includes interrupt and
exception delegation CSRs to direct the required interrupts and exceptions to Supervisor
mode. This capability is enabled by mideleg and medeleg
CSRs. Supervisor interrupts and exceptions can be managed via supervisor interrupt CSRs
stvec, sip, sie, and
scause. Machine mode software can also directly write to the sip
register to pend an interrupt to Supervisor mode. A typical use case is the timer and
software interrupts, which may have be to handled in both Machine and Supervisor modes. For
more information about RISC-V supervisor interrupts, see The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10.
By setting the corresponding bits in the mideleg and
medeleg CSRs, the Machine mode software can delegate the required
interrupts and exceptions to Supervisor mode. Once a delegated trap is asserted,
mcause is copied into scause and mepc
is copied into sepc, and then, the Hart traps to the
stvec address in Supervisor mode. Local interrupts can not be delegated
to Supervisor mode. The register description of the delegation and supervisor CSRs are
described in the following sections.