Overview

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GEM is accessed by the CPU Core Complex through the AXI Switch using the following interfaces:

GEM can be configured for SGMII or MII/GMII. The MII/GMII is only connected to the FPGA fabric. The PCS sub-block performs the 8b/10b operation for SGMII. SGMII is connected to the I/O BANK 5. Management Data Input/Output (MDIO) interface signals can be routed either from the FPGA fabric or from a dedicated MSSIO. The external PHY registers are configured using management interface (MDIO) of the GEM.

The following figure shows a high-level block diagram of GEM blocks.

Figure 1. High-Level Block Diagram