Interrupt CSRs

When a Hart receives an interrupt, the following events are executed:

1.The value of mstatus.MIE field is copied into mstatus.MPIE, then mstatus.MIE is cleared, effectively disabling interrupts.
2.The current value in the program counter (PC) is copied to the mepc register, and then PC is set to the value of mtvec. If vectored interrupts are enabled, PC is set to  mtvec.BASE + 4 × exception code.
3.The Privilege mode prior to the interrupt is encoded in mstatus.MPP.
4.At this point, control is handed over to the software in the interrupt handler with interrupts disabled.

Interrupts can be re-enabled by explicitly setting mstatus.MIE, or by executing the MRET instruction to exit the handler. When the MRET instruction is executed:

1.The Privilege mode is set to the value encoded in mstatus.MPP.
2.The value of mstatus.MPIE is copied to mstatus.MIE.
3.The PC is set to the value of mepc.
4.At this point, control is handed over to software.

The Interrupt CSRs are described in the following sections. This document only describes the implementation of interrupt CSRs specific to CPU Core Complex. For a complete description of RISC-V interrupt behavior and how to access CSRs, see The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10.