The MSS includes two Segmentation blocks (SEG0 and SEG1) to enable the allocation of cached, non-cached, and trace regions in the DDR memory. This allocation depends on the amount of DDR memory physically connected. To point at a base address in the DDR memory, an address offset is added or subtracted from the DDR address provided by the CPU Core Complex. The AXI bus simply passes through the segmentation block, and the address is modified.
SEG0 and SEG1 are grouped into the address range of the MPU blocks (Table 1). SEG0 and SEG1 blocks have eight 32-bit segmentation registers. Five registers in SEG0 are reserved and three registers in SEG1 are reserved. The APB interface is used to access these segmentation registers. The following table lists the register map of SEG0 and SEG1.
Register | Function | SEG0 | SEG1 |
---|---|---|---|
0 | Cached access at 0x00_8000_0000 | Configurable | Reserved |
1 | Cached access at 0x10_0000_0000 | Configurable | Reserved |
2 | Non-Cached access at 0x00_c000_0000 | Reserved | Configurable |
3 | Non-Cached access at 0x14_0000_000 | Reserved | Configurable |
4 | Non-Cached WCB access at 0x00_d000_0000 | Reserved | Configurable |
5 | Non-Cached WCB access at 0x18_0000_000 | Reserved | Configurable |
6 | Trace access | Reserved | Configurable |
7 | DDRC Blocker Control (Table 3) | Configurable | Reserved |
The register format of SEG0 and SEG1 is same and the bit fields are described in the following table.
Bit Fields | Function | Description |
---|---|---|
31 | LOCKED | When set to '1' the configuration cannot be changed until a Reset occurs |
[30:15] | Reserved | — |
[14:0] | Address Offset | This field is used to set the offset that is
added to address bits [37:24] to convert the CPU Core Complex address to DDR
base address. Value is two’s complement allowing the value to be decremented. |
The following table describes the DDRC Blocker Control register.
SEG0 Reg | Bit | Type | Field | Description |
---|---|---|---|---|
7 (0x1c) | 0 | RW | UNBLOCK | It is cleared at Reset. When set to '1',
disables the blocker function allowing the L2 cache controller to access the
MSS DDR Controller. Once written to '1' the register cannot be written to 0, only an MSS Reset will clear the register |