mcause)When a trap is taken in the Machine mode, mcause is
written with a code indicating the event that caused the trap. When the event that caused
the trap is an interrupt, the most significant bit (MSb) of mcause is set
to 1, and the least significant bits (LSb) indicate the interrupt number, using the same
encoding as the bit positions in mip. For example, a Machine Timer
Interrupt causes mcause to be set to
0x8000_0000_0000_0007. mcause is also used to indicate
the cause of synchronous exceptions, in which case the MSb of mcause is
set to 0. This section provides the mcause register description and a list
of synchronous Exception codes.
| Bits | Field Name | Attributes | Description |
|---|---|---|---|
| [62:0] | Exception Code | WLRL | A code identifying the last exception. See Table 2 |
| 63 | Interrupt | WLRL | 1 if the trap was caused by an interrupt; 0 otherwise. |
| Interrupt | Exception Code | Description |
|---|---|---|
|
1 1 1 1 1 1 1 1 1 1 1 1 1 |
0 1 2 3 4 5 6 7 8 9 10 11 12-15 |
Reserved Supervisor software interrupt Reserved Machine software interrupt Reserved Supervisor timer interrupt Reserved Machine timer interrupt Reserved Supervisor Global interrupt Reserved Machine Global interrupt Reserved |
| 1 1 1 1 |
16 17 18-62 63 |
Local Interrupt 0 Local Interrupt 1 ... Local Interrupt 47 |
| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 |
Instruction address misaligned Instruction access fault Illegal Instruction Breakpoint Load address misaligned Load access fault Store/AMO address misaligned Store/AMO access fault Environment call from U-mode Environment call from S-mode Reserved Environment call from M-mode Instruction page fault Load page fault Reserved Store/AMO page fault Reserved |