Machine mode software interrupts per Hart are enabled by writing to the
control register msip. Each msip register is a 32-bit
long WARL register. The LSb of msip is reflected in the msip bit of the
mip register. Other bits in each msip register are
hardwired to zero. At Reset, msip registers are cleared to zero. Software
interrupts allow inter-processor core communication in multi-Hart systems by enabling Harts
to write to each other's msip bits.